msm: mdss: dsi: create dsi clock manager (be2f6d25) · Commits · e / devices / android_kernel_xiaomi_markw

drivers/video/msm/mdss/Makefile

+1 −0

Original line number	Diff line number	Diff line
		@@ -38,6 +38,7 @@ endif
		mdss-dsi-objs := mdss_dsi.o mdss_dsi_host.o mdss_dsi_cmd.o mdss_dsi_status.o
		mdss-dsi-objs += mdss_dsi_panel.o
		mdss-dsi-objs += msm_mdss_io_8974.o
		mdss-dsi-objs += mdss_dsi_clk.o
		obj-$(CONFIG_FB_MSM_MDSS) += mdss-dsi.o
		obj-$(CONFIG_FB_MSM_MDSS) += mdss_panel.o
		obj-$(CONFIG_FB_MSM_MDSS) += mdss_hdmi_util.o

drivers/video/msm/mdss/mdss_dsi.c

+272 −60

Original line number	Diff line number	Diff line
		@@ -1040,9 +1040,19 @@ static int mdss_dsi_off(struct mdss_panel_data *pdata, int power_state)
		goto panel_power_ctrl;
		}

		mdss_dsi_clk_ctrl(ctrl_pdata, DSI_LINK_CLKS, 0);
		/*
		* Link clocks should be turned off before PHY can be disabled.
		* For command mode panels, all clocks are turned off prior to reaching
		* here, so core clocks should be turned on before accessing hardware
		* registers. For video mode panel, turn off link clocks and then
		* disable PHY
		*/
		if (pdata->panel_info.type == MIPI_CMD_PANEL)
		mdss_dsi_clk_ctrl(ctrl_pdata, DSI_CORE_CLKS, 1);
		mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle,
		MDSS_DSI_CORE_CLK, MDSS_DSI_CLK_ON);
		else
		mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle,
		MDSS_DSI_LINK_CLK, MDSS_DSI_CLK_OFF);

		if (!pdata->panel_info.ulps_suspend_enabled) {
		/* disable DSI controller */
		@@ -1051,7 +1061,8 @@ static int mdss_dsi_off(struct mdss_panel_data *pdata, int power_state)
		/* disable DSI phy */
		mdss_dsi_phy_disable(ctrl_pdata);
		}
		mdss_dsi_clk_ctrl(ctrl_pdata, DSI_CORE_CLKS, 0);
		mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle,
		MDSS_DSI_CORE_CLK, MDSS_DSI_CLK_OFF);

		panel_power_ctrl:
		ret = mdss_dsi_panel_power_ctrl(pdata, power_state);
		@@ -1101,9 +1112,11 @@ int mdss_dsi_switch_mode(struct mdss_panel_data *pdata, int mode)
		return -EINVAL;
		}

		mdss_dsi_clk_ctrl(ctrl_pdata, DSI_ALL_CLKS, 1);
		mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle,
		MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_ON);
		ctrl_pdata->switch_mode(pdata, mode);
		mdss_dsi_clk_ctrl(ctrl_pdata, DSI_ALL_CLKS, 0);
		mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle,
		MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_OFF);

		pr_debug("%s, end\n", __func__);
		return 0;
		@@ -1126,11 +1139,13 @@ static int mdss_dsi_reconfig(struct mdss_panel_data *pdata, int mode)

		if (pinfo->dms_mode == DYNAMIC_MODE_SWITCH_IMMEDIATE) {
		/* reset DSI */
		mdss_dsi_clk_ctrl(ctrl_pdata, DSI_ALL_CLKS, 1);
		mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle,
		MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_ON);
		mdss_dsi_sw_reset(ctrl_pdata, true);
		mdss_dsi_ctrl_setup(ctrl_pdata);
		mdss_dsi_controller_cfg(true, pdata);
		mdss_dsi_clk_ctrl(ctrl_pdata, DSI_ALL_CLKS, 0);
		mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle,
		MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_OFF);
		}

		pr_debug("%s, end\n", __func__);
		@@ -1225,7 +1240,8 @@ int mdss_dsi_on(struct mdss_panel_data *pdata)
		* This is also enable the DSI core power block and reset/setup
		* DSI phy
		*/
		mdss_dsi_clk_ctrl(ctrl_pdata, DSI_ALL_CLKS, 1);
		mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle,
		MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_ON);
		mdss_dsi_sw_reset(ctrl_pdata, true);
		mdss_dsi_read_hw_revision(ctrl_pdata);

		@@ -1252,7 +1268,8 @@ int mdss_dsi_on(struct mdss_panel_data *pdata)
		}

		if (pdata->panel_info.type == MIPI_CMD_PANEL)
		mdss_dsi_clk_ctrl(ctrl_pdata, DSI_ALL_CLKS, 0);
		mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle,
		MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_OFF);

		end:
		pr_debug("%s-:\n", __func__);
		@@ -1341,9 +1358,11 @@ static int mdss_dsi_unblank(struct mdss_panel_data *pdata)
		if (mdss_dsi_is_ctrl_clk_master(ctrl_pdata))
		sctrl = mdss_dsi_get_ctrl_clk_slave();

		mdss_dsi_clk_ctrl(ctrl_pdata, DSI_ALL_CLKS, 1);
		mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle,
		MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_ON);
		if (sctrl)
		mdss_dsi_clk_ctrl(sctrl, DSI_ALL_CLKS, 1);
		mdss_dsi_clk_ctrl(sctrl, sctrl->dsi_clk_handle,
		MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_ON);

		if (pdata->panel_info.blank_state == MDSS_PANEL_BLANK_LOW_POWER) {
		pr_debug("%s: dsi_unblank with panel always on\n", __func__);
		@@ -1372,9 +1391,11 @@ static int mdss_dsi_unblank(struct mdss_panel_data *pdata)
		}

		error:
		mdss_dsi_clk_ctrl(ctrl_pdata, DSI_ALL_CLKS, 0);
		mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle,
		MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_OFF);
		if (sctrl)
		mdss_dsi_clk_ctrl(sctrl, DSI_ALL_CLKS, 0);
		mdss_dsi_clk_ctrl(sctrl, sctrl->dsi_clk_handle,
		MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_OFF);
		pr_debug("%s-:\n", __func__);

		return ret;
		@@ -1398,7 +1419,8 @@ static int mdss_dsi_blank(struct mdss_panel_data *pdata, int power_state)
		pr_debug("%s+: ctrl=%p ndx=%d power_state=%d\n",
		__func__, ctrl_pdata, ctrl_pdata->ndx, power_state);

		mdss_dsi_clk_ctrl(ctrl_pdata, DSI_ALL_CLKS, 1);
		mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle,
		MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_ON);

		if (mdss_panel_is_power_on_lp(power_state)) {
		pr_debug("%s: low power state requested\n", __func__);
		@@ -1448,7 +1470,8 @@ static int mdss_dsi_blank(struct mdss_panel_data *pdata, int power_state)
		}

		error:
		mdss_dsi_clk_ctrl(ctrl_pdata, DSI_ALL_CLKS, 0);
		mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle,
		MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_OFF);
		pr_debug("%s-:End\n", __func__);
		return ret;
		}
		@@ -1468,12 +1491,14 @@ static int mdss_dsi_post_panel_on(struct mdss_panel_data *pdata)
		pr_debug("%s+: ctrl=%p ndx=%d\n", __func__,
		ctrl_pdata, ctrl_pdata->ndx);

		mdss_dsi_clk_ctrl(ctrl_pdata, DSI_ALL_CLKS, 1);
		mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle,
		MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_ON);

		if (ctrl_pdata->post_panel_on)
		ctrl_pdata->post_panel_on(pdata);

		mdss_dsi_clk_ctrl(ctrl_pdata, DSI_ALL_CLKS, 0);
		mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle,
		MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_OFF);
		pr_debug("%s-:\n", __func__);

		return 0;
		@@ -1680,15 +1705,16 @@ static int __mdss_dsi_dfps_update_clks(struct mdss_panel_data *pdata,
		clk_set_parent(ctrl_pdata->mux_pixel_clk,
		ctrl_pdata->shadow_pixel_clk);

		rc = clk_set_rate(ctrl_pdata->byte_clk,
		ctrl_pdata->byte_clk_rate);
		rc = mdss_dsi_clk_set_link_rate(ctrl_pdata->dsi_clk_handle,
		MDSS_DSI_LINK_BYTE_CLK, ctrl_pdata->byte_clk_rate, 0);
		if (rc) {
		pr_err("%s: dsi_byte_clk - clk_set_rate failed\n",
		__func__);
		return rc;
		}

		rc = clk_set_rate(ctrl_pdata->pixel_clk, ctrl_pdata->pclk_rate);
		rc = mdss_dsi_clk_set_link_rate(ctrl_pdata->dsi_clk_handle,
		MDSS_DSI_LINK_PIX_CLK, ctrl_pdata->pclk_rate, 0);
		if (rc) {
		pr_err("%s: dsi_pixel_clk - clk_set_rate failed\n",
		__func__);
		@@ -1718,6 +1744,23 @@ static int __mdss_dsi_dfps_update_clks(struct mdss_panel_data *pdata,
		clk_rate = pdata->panel_info.clk_rate;
		do_div(clk_rate, 8U);
		ctrl_pdata->byte_clk_rate = (u32) clk_rate;
		rc = mdss_dsi_clk_set_link_rate(ctrl_pdata->dsi_clk_handle,
		MDSS_DSI_LINK_BYTE_CLK, ctrl_pdata->byte_clk_rate,
		MDSS_DSI_CLK_UPDATE_CLK_RATE_AT_ON);
		if (rc) {
		pr_err("%s: dsi_byte_clk - clk_set_rate failed\n",
		__func__);
		return rc;
		}

		rc = mdss_dsi_clk_set_link_rate(ctrl_pdata->dsi_clk_handle,
		MDSS_DSI_LINK_PIX_CLK, ctrl_pdata->pclk_rate,
		MDSS_DSI_CLK_UPDATE_CLK_RATE_AT_ON);
		if (rc) {
		pr_err("%s: dsi_pixel_clk - clk_set_rate failed\n",
		__func__);
		return rc;
		}
		}

		return rc;
		@@ -1900,7 +1943,8 @@ static int mdss_dsi_reset_write_ptr(struct mdss_panel_data *pdata)
		panel_data);

		pinfo = &ctrl_pdata->panel_data.panel_info;
		mdss_dsi_clk_ctrl(ctrl_pdata, DSI_ALL_CLKS, 1);
		mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle,
		MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_ON);
		/* Need to reset the DSI core since the pixel stream was stopped. */
		mdss_dsi_sw_reset(ctrl_pdata, true);

		@@ -1926,7 +1970,8 @@ static int mdss_dsi_reset_write_ptr(struct mdss_panel_data *pdata)
		rc = ctrl_pdata->set_col_page_addr(pdata, true);

		skip_cmd_send:
		mdss_dsi_clk_ctrl(ctrl_pdata, DSI_ALL_CLKS, 0);
		mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle,
		MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_OFF);

		pr_debug("%s: DSI%d write ptr reset finished\n", __func__,
		ctrl_pdata->ndx);
		@@ -1962,6 +2007,24 @@ static int mdss_dsi_clk_refresh(struct mdss_panel_data *pdata)
		ctrl_pdata->byte_clk_rate = pdata->panel_info.clk_rate / 8;
		pr_debug("%s ctrl_pdata->byte_clk_rate=%d ctrl_pdata->pclk_rate=%d\n",
		__func__, ctrl_pdata->byte_clk_rate, ctrl_pdata->pclk_rate);

		rc = mdss_dsi_clk_set_link_rate(ctrl_pdata->dsi_clk_handle,
		MDSS_DSI_LINK_BYTE_CLK, ctrl_pdata->byte_clk_rate,
		MDSS_DSI_CLK_UPDATE_CLK_RATE_AT_ON);
		if (rc) {
		pr_err("%s: dsi_byte_clk - clk_set_rate failed\n",
		__func__);
		return rc;
		}

		rc = mdss_dsi_clk_set_link_rate(ctrl_pdata->dsi_clk_handle,
		MDSS_DSI_LINK_PIX_CLK, ctrl_pdata->pclk_rate,
		MDSS_DSI_CLK_UPDATE_CLK_RATE_AT_ON);
		if (rc) {
		pr_err("%s: dsi_pixel_clk - clk_set_rate failed\n",
		__func__);
		return rc;
		}
		return rc;
		}

		@@ -2262,11 +2325,173 @@ static struct device_node mdss_dsi_config_panel(struct platform_device pdev)
		return dsi_pan_node;
		}

		static int mdss_dsi_ctrl_clock_init(struct platform_device *ctrl_pdev,
		struct mdss_dsi_ctrl_pdata *ctrl_pdata)
		{
		int rc = 0;
		struct mdss_dsi_clk_info info;
		struct mdss_panel_info *pinfo;
		struct mdss_dsi_clk_client client1 = {"dsi_clk_client"};
		struct mdss_dsi_clk_client client2 = {"mdp_event_client"};
		void *handle;

		if (mdss_dsi_link_clk_init(ctrl_pdev, ctrl_pdata)) {
		pr_err("%s: unable to initialize Dsi ctrl clks\n", __func__);
		return -EPERM;
		}

		pinfo = &(ctrl_pdata->panel_data.panel_info);

		if (pinfo->dynamic_fps &&
		pinfo->dfps_update == DFPS_IMMEDIATE_CLK_UPDATE_MODE) {
		if (mdss_dsi_shadow_clk_init(ctrl_pdev, ctrl_pdata)) {
		pr_err("unable to initialize shadow ctrl clks\n");
		rc = -EPERM;
		goto error_link_clk_deinit;
		}
		}

		memset(&info, 0x0, sizeof(info));

		info.core_clks.mdp_core_clk = ctrl_pdata->shared_data->mdp_core_clk;
		info.core_clks.ahb_clk = ctrl_pdata->shared_data->ahb_clk;
		info.core_clks.axi_clk = ctrl_pdata->shared_data->axi_clk;
		info.core_clks.mmss_misc_ahb_clk =
		ctrl_pdata->shared_data->mmss_misc_ahb_clk;

		info.link_clks.esc_clk = ctrl_pdata->esc_clk;
		info.link_clks.byte_clk = ctrl_pdata->byte_clk;
		info.link_clks.pixel_clk = ctrl_pdata->pixel_clk;

		info.pre_clkoff_cb = mdss_dsi_pre_clkoff_cb;
		info.post_clkon_cb = mdss_dsi_post_clkon_cb;
		info.pre_clkon_cb = mdss_dsi_pre_clkon_cb;
		info.post_clkoff_cb = mdss_dsi_post_clkoff_cb;
		info.priv_data = ctrl_pdata;
		snprintf(info.name, DSI_CLK_NAME_LEN, "DSI%d", ctrl_pdata->ndx);
		ctrl_pdata->clk_mngr = mdss_dsi_clk_init(&info);
		if (IS_ERR_OR_NULL(ctrl_pdata->clk_mngr)) {
		rc = PTR_ERR(ctrl_pdata->clk_mngr);
		ctrl_pdata->clk_mngr = NULL;
		pr_err("dsi clock registration failed, rc = %d\n", rc);
		goto error_shadow_clk_deinit;
		}

		/*
		* There are two clients that control dsi clocks. MDP driver controls
		* the clock through MDSS_PANEL_EVENT_CLK_CTRL event and dsi driver
		* through clock interface. To differentiate between the votes from the
		* two clients, dsi driver will use two different handles to vote for
		* clock states from dsi and mdp driver.
		*/
		handle = mdss_dsi_clk_register(ctrl_pdata->clk_mngr, &client1);
		if (IS_ERR_OR_NULL(handle)) {
		rc = PTR_ERR(handle);
		pr_err("failed to register %s client, rc = %d\n",
		client1.client_name, rc);
		goto error_clk_deinit;
		} else {
		ctrl_pdata->dsi_clk_handle = handle;
		}

		handle = mdss_dsi_clk_register(ctrl_pdata->clk_mngr, &client2);
		if (IS_ERR_OR_NULL(handle)) {
		rc = PTR_ERR(handle);
		pr_err("failed to register %s client, rc = %d\n",
		client2.client_name, rc);
		goto error_clk_client_deregister;
		} else {
		ctrl_pdata->mdp_clk_handle = handle;
		}

		return rc;
		error_clk_client_deregister:
		mdss_dsi_clk_deregister(ctrl_pdata->dsi_clk_handle);
		error_clk_deinit:
		mdss_dsi_clk_deinit(ctrl_pdata);
		error_shadow_clk_deinit:
		mdss_dsi_shadow_clk_deinit(&ctrl_pdev->dev, ctrl_pdata);
		error_link_clk_deinit:
		mdss_dsi_link_clk_deinit(&ctrl_pdev->dev, ctrl_pdata);
		return rc;
		}

		static int mdss_dsi_set_clk_rates(struct mdss_dsi_ctrl_pdata *ctrl_pdata)
		{
		int rc = 0;

		rc = mdss_dsi_clk_set_link_rate(ctrl_pdata->dsi_clk_handle,
		MDSS_DSI_LINK_BYTE_CLK,
		ctrl_pdata->byte_clk_rate,
		MDSS_DSI_CLK_UPDATE_CLK_RATE_AT_ON);
		if (rc) {
		pr_err("%s: dsi_byte_clk - clk_set_rate failed\n",
		__func__);
		return rc;
		}

		rc = mdss_dsi_clk_set_link_rate(ctrl_pdata->dsi_clk_handle,
		MDSS_DSI_LINK_PIX_CLK,
		ctrl_pdata->pclk_rate,
		MDSS_DSI_CLK_UPDATE_CLK_RATE_AT_ON);
		if (rc) {
		pr_err("%s: dsi_pixel_clk - clk_set_rate failed\n",
		__func__);
		return rc;
		}

		rc = mdss_dsi_clk_set_link_rate(ctrl_pdata->dsi_clk_handle,
		MDSS_DSI_LINK_ESC_CLK,
		19200000,
		MDSS_DSI_CLK_UPDATE_CLK_RATE_AT_ON);
		if (rc) {
		pr_err("%s: dsi_esc_clk - clk_set_rate failed\n",
		__func__);
		return rc;
		}

		return rc;
		}

		static int mdss_dsi_cont_splash_config(struct mdss_panel_info *pinfo,
		struct mdss_dsi_ctrl_pdata *ctrl_pdata)
		{
		void *clk_handle;
		int rc = 0;

		if (pinfo->cont_splash_enabled) {
		rc = mdss_dsi_panel_power_ctrl(&(ctrl_pdata->panel_data),
		MDSS_PANEL_POWER_ON);
		if (rc) {
		pr_err("%s: Panel power on failed\n", __func__);
		return rc;
		}
		if (ctrl_pdata->bklt_ctrl == BL_PWM)
		mdss_dsi_panel_pwm_enable(ctrl_pdata);
		pinfo->blank_state = MDSS_PANEL_BLANK_UNBLANK;
		if (ctrl_pdata->panel_data.panel_info.type == MIPI_CMD_PANEL)
		clk_handle = ctrl_pdata->mdp_clk_handle;
		else
		clk_handle = ctrl_pdata->dsi_clk_handle;

		mdss_dsi_clk_ctrl(ctrl_pdata, clk_handle,
		MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_ON);
		ctrl_pdata->is_phyreg_enabled = 1;
		ctrl_pdata->ctrl_state \|=
		(CTRL_STATE_PANEL_INIT \| CTRL_STATE_MDP_ACTIVE);
		} else {
		pinfo->panel_power_state = MDSS_PANEL_POWER_OFF;
		}

		return rc;
		}

		static int mdss_dsi_ctrl_probe(struct platform_device *pdev)
		{
		int rc = 0;
		u32 index;
		struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
		struct mdss_panel_info *pinfo = NULL;
		struct device_node *dsi_pan_node = NULL;
		const char *ctrl_name;
		struct mdss_util_intf *util;
		@@ -2346,6 +2571,24 @@ static int mdss_dsi_ctrl_probe(struct platform_device *pdev)
		goto error_pan_node;
		}

		if (mdss_dsi_ctrl_clock_init(pdev, ctrl_pdata)) {
		pr_err("%s: unable to initialize dsi clk manager\n", __func__);
		return -EPERM;
		}

		rc = mdss_dsi_set_clk_rates(ctrl_pdata);
		if (rc) {
		pr_err("%s: Failed to set dsi clk rates\n", __func__);
		return rc;
		}

		pinfo = &(ctrl_pdata->panel_data.panel_info);
		rc = mdss_dsi_cont_splash_config(pinfo, ctrl_pdata);
		if (rc) {
		pr_err("%s: Failed to set dsi splash config\n", __func__);
		return rc;
		}

		if (mdss_dsi_is_te_based_esd(ctrl_pdata)) {
		rc = devm_request_irq(&pdev->dev,
		gpio_to_irq(ctrl_pdata->disp_te_gpio),
		@@ -3035,6 +3278,13 @@ int dsi_panel_device_register(struct platform_device *ctrl_pdev,
		pr_err("%s: unable to initialize the clk dividers\n", __func__);
		return rc;
		}
		ctrl_pdata->pclk_rate = mipi->dsi_pclk_rate;
		clk_rate = pinfo->clk_rate;
		do_div(clk_rate, 8U);
		ctrl_pdata->byte_clk_rate = (u32)clk_rate;
		pr_debug("%s: pclk=%d, bclk=%d\n", __func__,
		ctrl_pdata->pclk_rate, ctrl_pdata->byte_clk_rate);


		rc = mdss_dsi_get_dt_vreg_data(&ctrl_pdev->dev, pan_node,
		&ctrl_pdata->panel_power_data, DSI_PANEL_PM);
		@@ -3070,19 +3320,6 @@ int dsi_panel_device_register(struct platform_device *ctrl_pdev,
		return rc;
		}

		if (mdss_dsi_link_clk_init(ctrl_pdev, ctrl_pdata)) {
		pr_err("%s: unable to initialize Dsi ctrl clks\n", __func__);
		return -EPERM;
		}

		if (pinfo->dynamic_fps &&
		pinfo->dfps_update == DFPS_IMMEDIATE_CLK_UPDATE_MODE) {
		if (mdss_dsi_shadow_clk_init(ctrl_pdev, ctrl_pdata)) {
		pr_err("unable to initialize shadow ctrl clks\n");
		return -EPERM;
		}
		}

		if (mdss_dsi_retrieve_ctrl_resources(ctrl_pdev,
		pinfo->pdest,
		ctrl_pdata)) {
		@@ -3125,14 +3362,6 @@ int dsi_panel_device_register(struct platform_device *ctrl_pdev,
		return rc;
		}
		}

		ctrl_pdata->pclk_rate = mipi->dsi_pclk_rate;
		clk_rate = pinfo->clk_rate;
		do_div(clk_rate, 8U);
		ctrl_pdata->byte_clk_rate = (u32)clk_rate;
		pr_debug("%s: pclk=%d, bclk=%d\n", __func__,
		ctrl_pdata->pclk_rate, ctrl_pdata->byte_clk_rate);

		ctrl_pdata->ctrl_state = CTRL_STATE_UNKNOWN;

		/*
		@@ -3154,23 +3383,6 @@ int dsi_panel_device_register(struct platform_device *ctrl_pdev,
		}
		}

		if (pinfo->cont_splash_enabled) {
		rc = mdss_dsi_panel_power_ctrl(&(ctrl_pdata->panel_data),
		MDSS_PANEL_POWER_ON);
		if (rc) {
		pr_err("%s: Panel power on failed\n", __func__);
		return rc;
		}
		if (ctrl_pdata->bklt_ctrl == BL_PWM)
		mdss_dsi_panel_pwm_enable(ctrl_pdata);
		pinfo->blank_state = MDSS_PANEL_BLANK_UNBLANK;
		mdss_dsi_clk_ctrl(ctrl_pdata, DSI_ALL_CLKS, 1);
		ctrl_pdata->is_phyreg_enabled = 1;
		ctrl_pdata->ctrl_state \|=
		(CTRL_STATE_PANEL_INIT \| CTRL_STATE_MDP_ACTIVE);
		} else {
		pinfo->panel_power_state = MDSS_PANEL_POWER_OFF;
		}

		rc = mdss_register_panel(ctrl_pdev, &(ctrl_pdata->panel_data));
		if (rc) {

drivers/video/msm/mdss/mdss_dsi.h

+19 −8

Original line number	Diff line number	Diff line
		@@ -22,6 +22,7 @@

		#include "mdss_panel.h"
		#include "mdss_dsi_cmd.h"
		#include "mdss_dsi_clk.h"

		#define MMSS_SERDES_BASE_PHY 0x04f01000 /* mmss (De)Serializer CFG */

		@@ -328,10 +329,6 @@ struct panel_horizontal_idle {
		#define DSI_CTRL_CLK_SLAVE DSI_CTRL_RIGHT
		#define DSI_CTRL_CLK_MASTER DSI_CTRL_LEFT

		#define DSI_CORE_CLKS BIT(0)
		#define DSI_LINK_CLKS BIT(1)
		#define DSI_ALL_CLKS ((DSI_CORE_CLKS) \| (DSI_LINK_CLKS))

		#define DSI_EV_PLL_UNLOCKED 0x0001
		#define DSI_EV_MDP_FIFO_UNDERFLOW 0x0002
		#define DSI_EV_DSI_FIFO_EMPTY 0x0004
		@@ -366,8 +363,6 @@ struct mdss_dsi_ctrl_pdata {
		struct dss_io_data phy_io;
		struct dss_io_data phy_regulator_io;
		int reg_size;
		u32 core_clk_cnt;
		u32 link_clk_cnt;
		u32 flags;
		struct clk *byte_clk;
		struct clk *esc_clk;
		@@ -472,6 +467,10 @@ struct mdss_dsi_ctrl_pdata {
		struct mdss_util_intf *mdss_util;
		struct dsi_shared_data *shared_data;

		void *clk_mngr;
		void *dsi_clk_handle;
		void *mdp_clk_handle;
		int m_vote_cnt;
		/* debugfs structure */
		struct mdss_dsi_debugfs_info *debugfs_info;
		};
		@@ -501,8 +500,8 @@ void mdp4_dsi_cmd_trigger(void);
		void mdss_dsi_cmd_mdp_start(struct mdss_dsi_ctrl_pdata *ctrl);
		void mdss_dsi_cmd_bta_sw_trigger(struct mdss_panel_data *pdata);
		void mdss_dsi_ack_err_status(struct mdss_dsi_ctrl_pdata *ctrl);
		int mdss_dsi_clk_ctrl(struct mdss_dsi_ctrl_pdata *ctrl,
		u8 clk_type, int enable);
		int mdss_dsi_clk_ctrl(struct mdss_dsi_ctrl_pdata ctrl, void clk_handle,
		enum mdss_dsi_clk_type clk_type, enum mdss_dsi_clk_state clk_state);
		void mdss_dsi_clk_req(struct mdss_dsi_ctrl_pdata *ctrl,
		int enable);
		void mdss_dsi_controller_cfg(int enable,
		@@ -528,6 +527,18 @@ int mdss_dsi_shadow_clk_init(struct platform_device *pdev,
		struct mdss_dsi_ctrl_pdata *ctrl_pdata);
		void mdss_dsi_shadow_clk_deinit(struct device *dev,
		struct mdss_dsi_ctrl_pdata *ctrl_pdata);
		int mdss_dsi_pre_clkoff_cb(void *priv,
		enum mdss_dsi_clk_type clk_type,
		enum mdss_dsi_clk_state new_state);
		int mdss_dsi_post_clkoff_cb(void *priv,
		enum mdss_dsi_clk_type clk_type,
		enum mdss_dsi_clk_state curr_state);
		int mdss_dsi_post_clkon_cb(void *priv,
		enum mdss_dsi_clk_type clk_type,
		enum mdss_dsi_clk_state curr_state);
		int mdss_dsi_pre_clkon_cb(void *priv,
		enum mdss_dsi_clk_type clk_type,
		enum mdss_dsi_clk_state new_state);
		int mdss_dsi_panel_reset(struct mdss_panel_data *pdata, int enable);
		void mdss_dsi_phy_disable(struct mdss_dsi_ctrl_pdata *ctrl);
		void mdss_dsi_cmd_test_pattern(struct mdss_dsi_ctrl_pdata *ctrl);

drivers/video/msm/mdss/mdss_dsi_clk.c

0 → 100644

+957 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/video/msm/mdss/mdss_dsi_clk.h

0 → 100644

+228 −0

Original line number	Diff line number	Diff line
		/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		* only version 2 as published by the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*
		*/

		#ifndef _MDSS_DSI_CLK_H_
		#define _MDSS_DSI_CLK_H_

		#include <linux/mdss_io_util.h>
		#include <linux/list.h>

		#define DSI_CLK_NAME_LEN 20

		#define MDSS_DSI_CLK_UPDATE_CLK_RATE_AT_ON 0x1

		enum mdss_dsi_clk_state {
		MDSS_DSI_CLK_OFF,
		MDSS_DSI_CLK_ON,
		MDSS_DSI_CLK_EARLY_GATE,
		};

		enum mdss_dsi_link_clk_type {
		MDSS_DSI_LINK_ESC_CLK,
		MDSS_DSI_LINK_BYTE_CLK,
		MDSS_DSI_LINK_PIX_CLK,
		MDSS_DSI_LINK_CLK_MAX,
		};

		enum mdss_dsi_clk_type {
		MDSS_DSI_CORE_CLK = BIT(0),
		MDSS_DSI_LINK_CLK = BIT(1),
		MDSS_DSI_ALL_CLKS = (BIT(0) \| BIT(1)),
		MDSS_DSI_CLKS_MAX = BIT(2),
		};

		/**
		* typedef *pre_clockoff_cb() - Callback before clock is turned off
		* @priv: private data pointer.
		* @clk_type: clock which is being turned off.
		* @new_state: next state for the clock.
		*
		* @return: error code.
		*/
		typedef int (pre_clockoff_cb)(void priv,
		enum mdss_dsi_clk_type clk_type,
		enum mdss_dsi_clk_state new_state);

		/**
		* typedef *post_clockoff_cb() - Callback after clock is turned off
		* @priv: private data pointer.
		* @clk_type: clock which was turned off.
		* @curr_state: current state for the clock.
		*
		* @return: error code.
		*/
		typedef int (post_clockoff_cb)(void priv,
		enum mdss_dsi_clk_type clk_type,
		enum mdss_dsi_clk_state curr_state);

		/**
		* typedef *post_clockon_cb() - Callback after clock is turned on
		* @priv: private data pointer.
		* @clk_type: clock which was turned on.
		* @curr_state: current state for the clock.
		*
		* @return: error code.
		*/
		typedef int (post_clockon_cb)(void priv,
		enum mdss_dsi_clk_type clk_type,
		enum mdss_dsi_clk_state curr_state);

		/**
		* typedef *pre_clockon_cb() - Callback before clock is turned on
		* @priv: private data pointer.
		* @clk_type: clock which is being turned on.
		* @new_state: next state for the clock.
		*
		* @return: error code.
		*/
		typedef int (pre_clockon_cb)(void priv,
		enum mdss_dsi_clk_type clk_type,
		enum mdss_dsi_clk_state new_state);

		struct mdss_dsi_core_clk_info {
		struct clk *mdp_core_clk;
		struct clk *ahb_clk;
		struct clk *axi_clk;
		struct clk *mmss_misc_ahb_clk;
		};

		struct mdss_dsi_link_clk_info {
		struct clk *esc_clk;
		struct clk *byte_clk;
		struct clk *pixel_clk;
		};

		/**
		* struct mdss_dsi_clk_info - clock information to initialize manager
		* @name: name for the clocks to identify debug logs.
		* @core_clks: core clock information.
		* @link_clks: link clock information.
		* @pre_clkoff_cb: callback before a clock is turned off.
		* @post_clkoff_cb: callback after a clock is turned off.
		* @pre_clkon_cb: callback before a clock is turned on.
		* @post_clkon_cb: callback after a clock is turned on.
		* @priv_data: pointer to private data passed to callbacks.
		*/
		struct mdss_dsi_clk_info {
		char name[DSI_CLK_NAME_LEN];
		struct mdss_dsi_core_clk_info core_clks;
		struct mdss_dsi_link_clk_info link_clks;
		pre_clockoff_cb pre_clkoff_cb;
		post_clockoff_cb post_clkoff_cb;
		post_clockon_cb post_clkon_cb;
		pre_clockon_cb pre_clkon_cb;
		void *priv_data;
		};

		struct mdss_dsi_clk_client {
		char *client_name;
		};

		/**
		* mdss_dsi_clk_init() - Initializes clock manager
		* @info: Clock information to be managed by the clock manager.
		*
		* The Init API should be called during probe of the dsi driver. DSI driver
		* provides the clock handles to the core clocks and link clocks that will be
		* managed by the clock manager.
		*
		* returns handle or an error value.
		*/
		void mdss_dsi_clk_init(struct mdss_dsi_clk_info info);

		/**
		* mdss_dsi_clk_deinit() - Deinitializes the clock manager
		* @mngr: handle returned by mdss_dsi_clk_init().
		*
		* Deinit will turn off all the clocks and release all the resources acquired
		* by mdss_dsi_clk_init().
		*
		* @return: error code.
		*/
		int mdss_dsi_clk_deinit(void *mngr);

		/**
		* mdss_dsi_clk_register() - Register a client to control clock state
		* @mngr: handle returned by mdss_dsi_clk_init().
		* @client: client information.
		*
		* Register allows clients for DSI clock manager to acquire a handle which can
		* be used to request a specific clock state. The clock manager maintains a
		* reference count of the clock states requested by each client. Client has to
		* ensure that ON and OFF/EARLY_GATE calls are balanced properly.
		*
		* Requesting a particular clock state does not guarantee that physical clock
		* state. Physical clock state is determined by the states requested by all
		* clients.
		*
		* @return: handle or error code.
		*/
		void mdss_dsi_clk_register(void mngr, struct mdss_dsi_clk_client *client);

		/**
		* mdss_dsi_clk_deregister() - Deregister a registered client.
		* @client: client handle returned by mdss_dsi_clk_register().
		*
		* Deregister releases all resources acquired by mdss_dsi_clk_register().
		*
		* @return: error code.
		*/
		int mdss_dsi_clk_deregister(void *client);

		/**
		* mdss_dsi_clk_req_state() - Request a specific clock state
		* @client: client handle.
		* @clk: Type of clock requested (enum mdss_dsi_clk_type).
		* @state: clock state requested.
		*
		* This routine is used to request a new clock state for a specific clock. If
		* turning ON the clocks, this guarantees that clocks will be on before
		* returning. Valid state transitions are ON -> EARLY GATE, ON -> OFF,
		* EARLY GATE -> OFF, EARLY GATE -> ON and OFF -> ON.
		*
		* @return: error code.
		*/
		int mdss_dsi_clk_req_state(void *client, enum mdss_dsi_clk_type clk,
		enum mdss_dsi_clk_state state);

		/**
		* mdss_dsi_clk_set_link_rate() - set clock rate for link clocks
		* @client: client handle.
		* @clk: type of clock.
		* @rate: clock rate in Hz.
		* @flags: flags.
		*
		* This routine is used to request a specific clock rate. It supports an
		* additional flags argument which can change the behavior of the routine. If
		* MDSS_DSI_CLK_UPDATE_CLK_RATE_AT_ON flag is set, the routine caches the new
		* clock rate and applies it next time when the clock is turned on.
		*
		* @return: error code.
		*/
		int mdss_dsi_clk_set_link_rate(void *client, enum mdss_dsi_link_clk_type clk,
		u32 rate, u32 flags);

		/**
		* mdss_dsi_clk_force_toggle() - Turn off and turn on clocks
		* @client: client handle.
		* @clk: clock type.
		*
		* This routine has to be used in cases where clocks have to be toggled
		* irrespecitive of the refcount. This API bypasses the refcount and turns off
		* and turns on the clocks. This will fail if the clocks are in OFF state
		* already.
		*
		* @return:error code.
		*/
		int mdss_dsi_clk_force_toggle(void *client, u32 clk);
		#endif /* _MDSS_DSI_CLK_H_ */