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Commit bde83308 authored by Huaibin Yang's avatar Huaibin Yang Committed by Matt Wagantall
Browse files

clk: mdss: add delay for new pll locking sequence 



This change is corresponding to the update from h/w documentation.

Change-Id: I74ac06ce0cd1b0a8b52be6fa7dab123ebb2fc79e
Signed-off-by: default avatarHuaibin Yang <huaibiny@codeaurora.org>
parent 6d8d5717

drivers/clk/msm/mdss/mdss-dsi-20nm-pll-util.c

+1 −0
Original line number Diff line number Diff line
@@ -921,6 +921,7 @@ static void pll_20nm_config_vco_start(void __iomem *pll_base) 


	MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_PLL_VCOTAIL_EN, 0x03);

	MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_RESETSM_CNTRL3, 0x02);

	udelay(10);

	MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_RESETSM_CNTRL3, 0x03);

}