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Commit bdb2dfb2 authored by Rafał Miłecki's avatar Rafał Miłecki Committed by John W. Linville
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b43: HT-PHY: upload PHY values when switching channel 



After calibrating radio you can find few PHY writes in MMIO dumps:
 phy_read(0x0009) -> 0x0000
phy_write(0x01ce) <- 0x03dd
phy_write(0x01cf) <- 0x03d9
phy_write(0x01d0) <- 0x03d5
phy_write(0x01d1) <- 0x0424
phy_write(0x01d2) <- 0x0429
phy_write(0x01d3) <- 0x042d
By comparing to N-PHY code we found out that they are PHY tables for
channel switching plus band info read at the beginning.

Signed-off-by: default avatarRafał Miłecki <zajec5@gmail.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 1a931392

drivers/net/wireless/b43/phy_ht.c

+15 −1
Original line number Diff line number Diff line
@@ -82,9 +82,23 @@ static void b43_phy_ht_channel_setup(struct b43_wldev *dev, 
				const struct b43_phy_ht_channeltab_e_phy *e,

				struct ieee80211_channel *new_channel)

{

	bool old_band_5ghz;



	old_band_5ghz = b43_phy_read(dev, B43_PHY_HT_BANDCTL) & 0; /* FIXME */

	if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {

		/* TODO */

	} else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {

		/* TODO */

	}



	b43_phy_write(dev, B43_PHY_HT_BW1, e->bw1);

	b43_phy_write(dev, B43_PHY_HT_BW2, e->bw2);

	b43_phy_write(dev, B43_PHY_HT_BW3, e->bw3);

	b43_phy_write(dev, B43_PHY_HT_BW4, e->bw4);

	b43_phy_write(dev, B43_PHY_HT_BW5, e->bw5);

	b43_phy_write(dev, B43_PHY_HT_BW6, e->bw6);

}



static int b43_phy_ht_set_channel(struct b43_wldev *dev,

				  struct ieee80211_channel *channel,

				  enum nl80211_channel_type channel_type)

drivers/net/wireless/b43/phy_ht.h

+13 −1
Original line number Diff line number Diff line
@@ -4,9 +4,16 @@ 
#include "phy_common.h"





#define B43_PHY_HT_BANDCTL			0x009 /* Band control */

#define B43_PHY_HT_TABLE_ADDR			0x072 /* Table address */

#define B43_PHY_HT_TABLE_DATALO			0x073 /* Table data low */

#define B43_PHY_HT_TABLE_DATAHI			0x074 /* Table data high */

#define B43_PHY_HT_BW1				0x1CE

#define B43_PHY_HT_BW2				0x1CF

#define B43_PHY_HT_BW3				0x1D0

#define B43_PHY_HT_BW4				0x1D1

#define B43_PHY_HT_BW5				0x1D2

#define B43_PHY_HT_BW6				0x1D3



#define B43_PHY_HT_RF_CTL1			B43_PHY_EXTG(0x010)
@@ -20,7 +27,12 @@ 


/* Values for PHY registers used on channel switching */

struct b43_phy_ht_channeltab_e_phy {

	/* TODO */

	u16 bw1;

	u16 bw2;

	u16 bw3;

	u16 bw4;

	u16 bw5;

	u16 bw6;

};