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Commit bd737fea authored by Jean-Christophe PLAGNIOL-VILLARD's avatar Jean-Christophe PLAGNIOL-VILLARD Committed by Olof Johansson
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ARM: at91: sam9g45: shutdown ddr1 too when rebooting 



Like we are doing on DDR0 we need to cleanly shutdown DDR1 if it is
used before rebooting.
If DDR1 is not initialized, we check it and avoid dereferencing its address.
Even by adding two more instructions, we are able to complete the procedure
within a single cache line.

Signed-off-by: default avatarJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: default avatarNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parent 5abf58bf

arch/arm/mach-at91/at91sam9g45_reset.S

+8 −0
Original line number Diff line number Diff line
@@ -16,11 +16,17 @@ 
#include "at91_rstc.h"

			.arm



/*

 * at91_ramc_base is an array void*

 * init at NULL if only one DDR controler is present in or DT

 */

			.globl	at91sam9g45_restart



at91sam9g45_restart:

			ldr	r5, =at91_ramc_base		@ preload constants

			ldr	r0, [r5]

			ldr	r5, [r5, #4]			@ ddr1

			cmp	r5, #0

			ldr	r4, =at91_rstc_base

			ldr	r1, [r4]
@@ -30,6 +36,8 @@ at91sam9g45_restart: 


			.balign	32				@ align to cache line



			strne	r2, [r5, #AT91_DDRSDRC_RTR]	@ disable DDR1 access

			strne	r3, [r5, #AT91_DDRSDRC_LPR]	@ power down DDR1

			str	r2, [r0, #AT91_DDRSDRC_RTR]	@ disable DDR0 access

			str	r3, [r0, #AT91_DDRSDRC_LPR]	@ power down DDR0

			str	r4, [r1, #AT91_RSTC_CR]		@ reset processor