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Commit bd329233 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Update CPU clock fmax for MSMGold"

parents 4da19e9e 1d05fa9d

arch/arm/boot/dts/qcom/msmgold-regulator.dtsi

+5 −4
Original line number Diff line number Diff line
@@ -384,7 +384,7 @@ 
		interrupts = <0 15 0>;

		regulator-name = "apc_corner";

		regulator-min-microvolt = <1>;

		regulator-max-microvolt = <3>;

		regulator-max-microvolt = <4>;



		qcom,cpr-fuse-corners = <3>;

		qcom,cpr-voltage-ceiling = <1155000 1225000 1350000>;
@@ -421,11 +421,12 @@ 
					<70 54 7 0>;

		qcom,cpr-fuse-quot-offset-scale = <5 5 5>;

		qcom,cpr-init-voltage-step = <10000>;

		qcom,cpr-corner-map = <1 2 3>;

		qcom,cpr-corner-map = <1 2 3 3>;

		qcom,cpr-corner-frequency-map =

				<1 998400000>,

				<1 960000000>,

				<2 1094400000>,

				<3 1209600000>;

				<3 1248000000>,

				<4 1401000000>;

		qcom,speed-bin-fuse-sel = <37 34 3 0>;

		qcom,cpr-quot-adjust-scaling-factor-max = <0 1400 1400>;

		qcom,cpr-fuse-revision = <69 39 3 0>;

arch/arm/boot/dts/qcom/msmgold.dtsi

+6 −4
Original line number Diff line number Diff line
@@ -676,9 +676,10 @@ 
		clock-names = "clk-c1-4", "clk-c1-5";

		qcom,speed0-bin-v0-c1 =

			<          0 0>,

			<  998400000 1>,

			<  960000000 1>,

			< 1094400000 2>,

			< 1209600000 3>;

			< 1248000000 3>,

			< 1401000000 4>;



		#clock-cells = <1>;

	};
@@ -693,9 +694,10 @@ 
			 <&clock_cpu clk_a53_bc_clk>;



		qcom,cpufreq-table =

			 <  998400 >,

			 <  960000 >,

			 < 1094400 >,

			 < 1209600 >;

			 < 1248000 >,

			 < 1401000 >;

	};



	usb_otg: usb@78db000 {

drivers/clk/msm/clock-cpu-8939.c

+4 −3
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.

 * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -746,7 +746,7 @@ static int clock_a53_probe(struct platform_device *pdev) 
		clk_set_rate(&cci_clk.c, rate);

	}



	for (mux_id = 0; mux_id < A53SS_MUX_CCI; mux_id++) {

	for (mux_id = 0; mux_id < mux_num; mux_id++) {

		/* Force a PLL reconfiguration */

		config_pll(mux_id);

	}
@@ -762,6 +762,7 @@ static int clock_a53_probe(struct platform_device *pdev) 
	for_each_online_cpu(cpu) {

		WARN(clk_prepare_enable(&cpuclk[cpu/4]->c),

				"Unable to turn on CPU clock");

		if (!single_cluster)

			clk_prepare_enable(&cci_clk.c);

	}

	put_online_cpus();

drivers/clk/msm/clock-gcc-8952.c

+3 −2
Original line number Diff line number Diff line
@@ -473,6 +473,7 @@ static struct pll_vote_clk gpll4_clk_src = { 
		CLK_INIT(gpll4_clk_src.c),

	},

};

DEFINE_EXT_CLK(gpll4_out_clk_src, &gpll4_clk_src.c);



static struct clk_freq_tbl ftbl_gcc_camss_top_ahb_clk[] = {

	F( 40000000,	gpll0,	10,	1,	2),
@@ -601,7 +602,7 @@ static struct clk_freq_tbl ftbl_gcc_venus0_vcodec0_clk_gold[] = { 
	F( 200000000,          gpll0,    4,    0,     0),

	F( 270000000,          gpll6,    4,    0,     0),

	F( 308570000,          gpll6,  3.5,    0,     0),

	F( 329140000,          gpll4,  3.5,    0,     0),

	F( 329140000,          gpll4_out,  3.5,    0,     0),

	F( 360000000,          gpll6,    3,    0,     0),

	F_END

};
@@ -665,7 +666,7 @@ static struct clk_freq_tbl ftbl_gcc_camss_vfe0_1_clk_gold[] = { 
	F( 266670000,          gpll0,    3,    0,     0),

	F( 308570000,          gpll6,  3.5,    0,     0),

	F( 320000000,          gpll0,  2.5,    0,     0),

	F( 329140000,          gpll4,  3.5,    0,     0),

	F( 329140000,          gpll4_out,  3.5,    0,     0),

	F( 360000000,          gpll6,    3,    0,     0),

	F_END

};

include/dt-bindings/clock/msm-clocks-hwio-8952.h

+2 −1
Original line number Diff line number Diff line 
/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.

/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -283,6 +283,7 @@ 
/* cci_clk_src and usb_fs_system_clk_src */

#define gpll0_out_aux_source_val	2

#define gpll4_source_val		2   /* sdcc1_apss_clk_src */

#define gpll4_out_source_val		3   /* sdcc1_apss_clk_src */

#define gpll6_source_val		2   /* mclk0_2_clk_src */

#define gpll6_aux_source_val		3   /* gfx3d_clk_src */

#define gpll6_out_main_source_val	1   /* usb_fs_ic_clk_src */