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Commit bd1274dc authored by Russell King's avatar Russell King
Browse files

Merge branch 'v6v7' into devel 

Conflicts:
	arch/arm/include/asm/cacheflush.h
	arch/arm/include/asm/proc-fns.h
	arch/arm/mm/Kconfig
parents 1f0090a1 3ba6e69a

arch/arm/Kconfig

+8 −6
Original line number Diff line number Diff line
@@ -7,7 +7,7 @@ config ARM 
	select HAVE_MEMBLOCK

	select RTC_LIB

	select SYS_SUPPORTS_APM_EMULATION

	select GENERIC_ATOMIC64 if (!CPU_32v6K || !AEABI)

	select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)

	select HAVE_OPROFILE if (HAVE_PERF_EVENTS)

	select HAVE_ARCH_KGDB

	select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)
@@ -24,7 +24,7 @@ config ARM 
	select HAVE_PERF_EVENTS

	select PERF_USE_VMALLOC

	select HAVE_REGS_AND_STACK_ACCESS_API

	select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V7))

	select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))

	select HAVE_C_RECORDMCOUNT

	select HAVE_GENERIC_HARDIRQS

	select HAVE_SPARSE_IRQ
@@ -456,6 +456,7 @@ config ARCH_IXP4XX 


config ARCH_DOVE

	bool "Marvell Dove"

	select CPU_V6K

	select PCI

	select ARCH_REQUIRE_GPIOLIB

	select GENERIC_CLOCKEVENTS
@@ -1059,7 +1060,7 @@ config XSCALE_PMU 
	default y



config CPU_HAS_PMU

	depends on (CPU_V6 || CPU_V7 || XSCALE_PMU) && \

	depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \

		   (!ARCH_OMAP3 || OMAP3_EMU)

	default y

	bool
@@ -1075,7 +1076,7 @@ endif 


config ARM_ERRATA_411920

	bool "ARM errata: Invalidation of the Instruction Cache operation can fail"

	depends on CPU_V6

	depends on CPU_V6 || CPU_V6K

	help

	  Invalidation of the Instruction Cache operation can

	  fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
@@ -1318,6 +1319,7 @@ source "kernel/time/Kconfig" 
config SMP

	bool "Symmetric Multi-Processing (EXPERIMENTAL)"

	depends on EXPERIMENTAL

	depends on CPU_V6K || CPU_V7

	depends on GENERIC_CLOCKEVENTS

	depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \

		 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
@@ -1429,7 +1431,7 @@ config HZ 


config THUMB2_KERNEL

	bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"

	depends on CPU_V7 && !CPU_V6 && EXPERIMENTAL

	depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL

	select AEABI

	select ARM_ASM_UNIFIED

	help
@@ -1963,7 +1965,7 @@ config FPE_FASTFPE 


config VFP

	bool "VFP-format floating point maths"

	depends on CPU_V6 || CPU_ARM926T || CPU_V7 || CPU_FEROCEON

	depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON

	help

	  Say Y to include VFP support code in the kernel. This is needed

	  if your hardware includes a VFP unit.

arch/arm/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -89,6 +89,7 @@ tune-$(CONFIG_CPU_XSCALE) :=$(call cc-option,-mtune=xscale,-mtune=strongarm110) 
tune-$(CONFIG_CPU_XSC3)		:=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale

tune-$(CONFIG_CPU_FEROCEON)	:=$(call cc-option,-mtune=marvell-f,-mtune=xscale)

tune-$(CONFIG_CPU_V6)		:=$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm)

tune-$(CONFIG_CPU_V6K)		:=$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm)



ifeq ($(CONFIG_AEABI),y)

CFLAGS_ABI	:=-mabi=aapcs-linux -mno-thumb-interwork

arch/arm/boot/compressed/head.S

+1 −1
Original line number Diff line number Diff line
@@ -21,7 +21,7 @@ 


#if defined(CONFIG_DEBUG_ICEDCC)



#ifdef CONFIG_CPU_V6

#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)

		.macro	loadsp, rb, tmp

		.endm

		.macro	writeb, ch, rb

arch/arm/boot/compressed/misc.c

+1 −1
Original line number Diff line number Diff line
@@ -36,7 +36,7 @@ extern void error(char *x); 


#ifdef CONFIG_DEBUG_ICEDCC



#ifdef CONFIG_CPU_V6

#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)



static void icedcc_putc(int ch)

{

arch/arm/include/asm/bitops.h

+22 −38
Original line number Diff line number Diff line
@@ -148,15 +148,19 @@ ____atomic_test_and_change_bit(unsigned int bit, volatile unsigned long *p) 
 * Note that bit 0 is defined to be 32-bit word bit 0, not byte 0 bit 0.

 */



/*

 * Native endian assembly bitops.  nr = 0 -> word 0 bit 0.

 */

extern void _set_bit(int nr, volatile unsigned long * p);

extern void _clear_bit(int nr, volatile unsigned long * p);

extern void _change_bit(int nr, volatile unsigned long * p);

extern int _test_and_set_bit(int nr, volatile unsigned long * p);

extern int _test_and_clear_bit(int nr, volatile unsigned long * p);

extern int _test_and_change_bit(int nr, volatile unsigned long * p);



/*

 * Little endian assembly bitops.  nr = 0 -> byte 0 bit 0.

 */

extern void _set_bit_le(int nr, volatile unsigned long * p);

extern void _clear_bit_le(int nr, volatile unsigned long * p);

extern void _change_bit_le(int nr, volatile unsigned long * p);

extern int _test_and_set_bit_le(int nr, volatile unsigned long * p);

extern int _test_and_clear_bit_le(int nr, volatile unsigned long * p);

extern int _test_and_change_bit_le(int nr, volatile unsigned long * p);

extern int _find_first_zero_bit_le(const void * p, unsigned size);

extern int _find_next_zero_bit_le(const void * p, int size, int offset);

extern int _find_first_bit_le(const unsigned long *p, unsigned size);
@@ -165,12 +169,6 @@ extern int _find_next_bit_le(const unsigned long *p, int size, int offset); 
/*

 * Big endian assembly bitops.  nr = 0 -> byte 3 bit 0.

 */

extern void _set_bit_be(int nr, volatile unsigned long * p);

extern void _clear_bit_be(int nr, volatile unsigned long * p);

extern void _change_bit_be(int nr, volatile unsigned long * p);

extern int _test_and_set_bit_be(int nr, volatile unsigned long * p);

extern int _test_and_clear_bit_be(int nr, volatile unsigned long * p);

extern int _test_and_change_bit_be(int nr, volatile unsigned long * p);

extern int _find_first_zero_bit_be(const void * p, unsigned size);

extern int _find_next_zero_bit_be(const void * p, int size, int offset);

extern int _find_first_bit_be(const unsigned long *p, unsigned size);
@@ -180,33 +178,26 @@ extern int _find_next_bit_be(const unsigned long *p, int size, int offset); 
/*

 * The __* form of bitops are non-atomic and may be reordered.

 */

#define	ATOMIC_BITOP_LE(name,nr,p)		\

	(__builtin_constant_p(nr) ?		\

	 ____atomic_##name(nr, p) :		\

	 _##name##_le(nr,p))



#define	ATOMIC_BITOP_BE(name,nr,p)		\

	(__builtin_constant_p(nr) ?		\

	 ____atomic_##name(nr, p) :		\

	 _##name##_be(nr,p))

#define ATOMIC_BITOP(name,nr,p)			\

	(__builtin_constant_p(nr) ? ____atomic_##name(nr, p) : _##name(nr,p))

#else

#define ATOMIC_BITOP_LE(name,nr,p)	_##name##_le(nr,p)

#define ATOMIC_BITOP_BE(name,nr,p)	_##name##_be(nr,p)

#define ATOMIC_BITOP(name,nr,p)		_##name(nr,p)

#endif



#define NONATOMIC_BITOP(name,nr,p)		\

	(____nonatomic_##name(nr, p))

/*

 * Native endian atomic definitions.

 */

#define set_bit(nr,p)			ATOMIC_BITOP(set_bit,nr,p)

#define clear_bit(nr,p)			ATOMIC_BITOP(clear_bit,nr,p)

#define change_bit(nr,p)		ATOMIC_BITOP(change_bit,nr,p)

#define test_and_set_bit(nr,p)		ATOMIC_BITOP(test_and_set_bit,nr,p)

#define test_and_clear_bit(nr,p)	ATOMIC_BITOP(test_and_clear_bit,nr,p)

#define test_and_change_bit(nr,p)	ATOMIC_BITOP(test_and_change_bit,nr,p)



#ifndef __ARMEB__

/*

 * These are the little endian, atomic definitions.

 */

#define set_bit(nr,p)			ATOMIC_BITOP_LE(set_bit,nr,p)

#define clear_bit(nr,p)			ATOMIC_BITOP_LE(clear_bit,nr,p)

#define change_bit(nr,p)		ATOMIC_BITOP_LE(change_bit,nr,p)

#define test_and_set_bit(nr,p)		ATOMIC_BITOP_LE(test_and_set_bit,nr,p)

#define test_and_clear_bit(nr,p)	ATOMIC_BITOP_LE(test_and_clear_bit,nr,p)

#define test_and_change_bit(nr,p)	ATOMIC_BITOP_LE(test_and_change_bit,nr,p)

#define find_first_zero_bit(p,sz)	_find_first_zero_bit_le(p,sz)

#define find_next_zero_bit(p,sz,off)	_find_next_zero_bit_le(p,sz,off)

#define find_first_bit(p,sz)		_find_first_bit_le(p,sz)
@@ -215,16 +206,9 @@ extern int _find_next_bit_be(const unsigned long *p, int size, int offset); 
#define WORD_BITOFF_TO_LE(x)		((x))



#else



/*

 * These are the big endian, atomic definitions.

 */

#define set_bit(nr,p)			ATOMIC_BITOP_BE(set_bit,nr,p)

#define clear_bit(nr,p)			ATOMIC_BITOP_BE(clear_bit,nr,p)

#define change_bit(nr,p)		ATOMIC_BITOP_BE(change_bit,nr,p)

#define test_and_set_bit(nr,p)		ATOMIC_BITOP_BE(test_and_set_bit,nr,p)

#define test_and_clear_bit(nr,p)	ATOMIC_BITOP_BE(test_and_clear_bit,nr,p)

#define test_and_change_bit(nr,p)	ATOMIC_BITOP_BE(test_and_change_bit,nr,p)

#define find_first_zero_bit(p,sz)	_find_first_zero_bit_be(p,sz)

#define find_next_zero_bit(p,sz,off)	_find_next_zero_bit_be(p,sz,off)

#define find_first_bit(p,sz)		_find_first_bit_be(p,sz)