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Commit bd019727 authored by Hemant Kumar's avatar Hemant Kumar
Browse files

usb: qusb: Select QUSB2 clk source based on phy clk scheme 



In order to lock QUSB2 PHY PLL QUSB2PHY_PLL_TEST register needs
to be updated to indicate clk source based on the
TCSR PHY_SCHEME_SEL register value. If PHY_CLK_SCHEME_SEL bit is
set single ended clk scheme is selected otherwise differential
clk scheme is selected.

Change-Id: I946fe364c857d45cf3f3cacabd5788b826cad9f0
Signed-off-by: default avatarHemant Kumar <hemantk@codeaurora.org>
parent c2e38a43

Documentation/devicetree/bindings/usb/msm-phy.txt

+1 −0
Original line number Diff line number Diff line
@@ -154,6 +154,7 @@ Optional properties: 
   via the QSCRATCH interface.

   "emu_phy_base" : phy base address used for programming emulation target phy.

   "ref_clk_addr" : ref_clk bcr address used for on/off ref_clk before reset.

   "tcsr_phy_clk_scheme_sel": address used to determine QUSB PHY clk source.

 - reg-names: Should be "qscratch_base". The qscratch register bank

   allows us to manipulate QUSB PHY bits eg. to enable D+ pull-up using s/w

   control in device mode. The reg-names property is required if the

arch/arm/boot/dts/qcom/mdmcalifornium.dtsi

+4 −2
Original line number Diff line number Diff line
@@ -591,9 +591,11 @@ 
	qusb_phy: qusb@79000 {

		compatible = "qcom,qusb2phy";

		reg = <0x00079000 0x180>,

		      <0x08af8800 0x400>;

		      <0x08af8800 0x400>,

		      <0x01956044 0x4>;

		reg-names = "qusb_phy_base",

			    "qscratch_base";

			    "qscratch_base",

			    "tcsr_phy_clk_scheme_sel";

		vdd-supply = <&pmdcalifornium_l4>;

		vdda18-supply = <&pmdcalifornium_l5>;

		vdda33-supply = <&pmdcalifornium_l10>;

drivers/usb/phy/phy-msm-qusb.c

+35 −1
Original line number Diff line number Diff line
@@ -25,6 +25,9 @@ 
#include <linux/usb/phy.h>

#include <linux/usb/msm_hsusb.h>



/* TCSR_PHY_CLK_SCHEME_SEL bit mask */

#define PHY_CLK_SCHEME_SEL BIT(0)



#define QUSB2PHY_PLL_STATUS	0x38

#define QUSB2PHY_PLL_LOCK	BIT(5)
@@ -52,6 +55,9 @@ 
#define UTMI_ULPI_SEL			BIT(7)

#define UTMI_TEST_MUX_SEL		BIT(6)



#define QUSB2PHY_PLL_TEST		0x04

#define CLK_REF_SEL			BIT(7)



#define QUSB2PHY_PORT_TUNE1             0x80

#define QUSB2PHY_PORT_TUNE2             0x84

#define QUSB2PHY_PORT_TUNE3             0x88
@@ -99,6 +105,7 @@ struct qusb_phy { 
	void __iomem		*qscratch_base;

	void __iomem		*tune2_efuse_reg;

	void __iomem		*ref_clk_base;

	void __iomem		*tcsr_phy_clk_scheme_sel;



	struct clk		*ref_clk_src;

	struct clk		*ref_clk;
@@ -521,7 +528,7 @@ static void qusb_phy_write_seq(void __iomem *base, u32 *seq, int cnt, 
static int qusb_phy_init(struct usb_phy *phy)

{

	struct qusb_phy *qphy = container_of(phy, struct qusb_phy, phy);

	int ret;

	int ret, reset_val = 0;



	dev_dbg(phy->dev, "%s\n", __func__);
@@ -585,6 +592,9 @@ static int qusb_phy_init(struct usb_phy *phy) 
	if (qphy->ulpi_mode)

		writel_relaxed(0x0, qphy->base + QUSB2PHY_PORT_UTMI_CTRL2);



	/* save reset value to override based on clk scheme */

	reset_val = readl_relaxed(qphy->base + QUSB2PHY_PLL_TEST);



	if (qphy->qusb_phy_init_seq)

		qusb_phy_write_seq(qphy->base, qphy->qusb_phy_init_seq,

				qphy->init_seq_len, 0);
@@ -612,6 +622,21 @@ static int qusb_phy_init(struct usb_phy *phy) 
				qphy->base + QUSB2PHY_PORT_TUNE2);

	}



	if (qphy->tcsr_phy_clk_scheme_sel) {

		ret = readl_relaxed(qphy->tcsr_phy_clk_scheme_sel);

		if (ret & PHY_CLK_SCHEME_SEL) {

			pr_debug("%s:select single-ended clk src\n",

				__func__);

			reset_val |= CLK_REF_SEL;

		} else {

			pr_debug("%s:select differential clk src\n",

				__func__);

			reset_val &= ~CLK_REF_SEL;

		}



		writel_relaxed(reset_val, qphy->base + QUSB2PHY_PLL_TEST);

	}



	/* ensure above writes are completed before re-enabling PHY */

	wmb();
@@ -881,6 +906,15 @@ static int qusb_phy_probe(struct platform_device *pdev) 
			dev_dbg(dev, "ref_clk_address is not available.\n");

	}



	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,

			"tcsr_phy_clk_scheme_sel");

	if (res) {

		qphy->tcsr_phy_clk_scheme_sel = devm_ioremap_nocache(dev,

				res->start, resource_size(res));

		if (IS_ERR(qphy->tcsr_phy_clk_scheme_sel))

			dev_dbg(dev, "err reading tcsr_phy_clk_scheme_sel\n");

	}



	qphy->ref_clk_src = devm_clk_get(dev, "ref_clk_src");

	if (IS_ERR(qphy->ref_clk_src))

		return PTR_ERR(qphy->ref_clk_src);