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Commit bcdbbe3d authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge branch 'omap/fixes-non-critical-part2' into next/fixes-non-critical 

* omap/fixes-non-critical-part2:
  ARM: OMAP4: clock: Add CPU local timer clock node
  ARM: OMAP4: hwmod: Don't wait for the idle status if modulemode is not supported
  ARM: OMAP: AM3517/3505: fix crash on boot due to incorrect voltagedomain data
parents 53bf82ce 30c95692

arch/arm/mach-omap2/clock44xx_data.c

+9 −0
Original line number Diff line number Diff line
@@ -1206,6 +1206,14 @@ static const struct clksel ocp_abe_iclk_div[] = { 
	{ .parent = NULL },

};



static struct clk mpu_periphclk = {

	.name		= "mpu_periphclk",

	.parent		= &dpll_mpu_ck,

	.ops		= &clkops_null,

	.fixed_div	= 2,

	.recalc		= &omap_fixed_divisor_recalc,

};



static struct clk ocp_abe_iclk = {

	.name		= "ocp_abe_iclk",

	.parent		= &aess_fclk,
@@ -3189,6 +3197,7 @@ static struct omap_clk omap44xx_clks[] = { 
	CLK(NULL,	"l4_div_ck",			&l4_div_ck,	CK_443X),

	CLK(NULL,	"lp_clk_div_ck",		&lp_clk_div_ck,	CK_443X),

	CLK(NULL,	"l4_wkup_clk_mux_ck",		&l4_wkup_clk_mux_ck,	CK_443X),

	CLK("smp_twd",	NULL,				&mpu_periphclk,	CK_443X),

	CLK(NULL,	"ocp_abe_iclk",			&ocp_abe_iclk,	CK_443X),

	CLK(NULL,	"per_abe_24m_fclk",		&per_abe_24m_fclk,	CK_443X),

	CLK(NULL,	"per_abe_nc_fclk",		&per_abe_nc_fclk,	CK_443X),

arch/arm/mach-omap2/omap_hwmod.c

+49 −49
Original line number Diff line number Diff line
@@ -706,27 +706,65 @@ static void _enable_module(struct omap_hwmod *oh) 
}



/**

 * _disable_module - enable CLKCTRL modulemode on OMAP4

 * _omap4_wait_target_disable - wait for a module to be disabled on OMAP4

 * @oh: struct omap_hwmod *

 *

 * Wait for a module @oh to enter slave idle.  Returns 0 if the module

 * does not have an IDLEST bit or if the module successfully enters

 * slave idle; otherwise, pass along the return value of the

 * appropriate *_cm*_wait_module_idle() function.

 */

static int _omap4_wait_target_disable(struct omap_hwmod *oh)

{

	if (!cpu_is_omap44xx())

		return 0;



	if (!oh)

		return -EINVAL;



	if (oh->_int_flags & _HWMOD_NO_MPU_PORT)

		return 0;



	if (oh->flags & HWMOD_NO_IDLEST)

		return 0;



	return omap4_cminst_wait_module_idle(oh->clkdm->prcm_partition,

					     oh->clkdm->cm_inst,

					     oh->clkdm->clkdm_offs,

					     oh->prcm.omap4.clkctrl_offs);

}



/**

 * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4

 * @oh: struct omap_hwmod *

 *

 * Disable the PRCM module mode related to the hwmod @oh.

 * No return value.

 * Return EINVAL if the modulemode is not supported and 0 in case of success.

 */

static void _disable_module(struct omap_hwmod *oh)

static int _omap4_disable_module(struct omap_hwmod *oh)

{

	int v;



	/* The module mode does not exist prior OMAP4 */

	if (cpu_is_omap24xx() || cpu_is_omap34xx())

		return;

	if (!cpu_is_omap44xx())

		return -EINVAL;



	if (!oh->clkdm || !oh->prcm.omap4.modulemode)

		return;

		return -EINVAL;



	pr_debug("omap_hwmod: %s: _disable_module\n", oh->name);

	pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__);



	omap4_cminst_module_disable(oh->clkdm->prcm_partition,

				    oh->clkdm->cm_inst,

				    oh->clkdm->clkdm_offs,

				    oh->prcm.omap4.clkctrl_offs);



	v = _omap4_wait_target_disable(oh);

	if (v)

		pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",

			oh->name);



	return 0;

}



/**
@@ -1152,36 +1190,6 @@ static int _wait_target_ready(struct omap_hwmod *oh) 
	return ret;

}



/**

 * _wait_target_disable - wait for a module to be disabled

 * @oh: struct omap_hwmod *

 *

 * Wait for a module @oh to enter slave idle.  Returns 0 if the module

 * does not have an IDLEST bit or if the module successfully enters

 * slave idle; otherwise, pass along the return value of the

 * appropriate *_cm*_wait_module_idle() function.

 */

static int _wait_target_disable(struct omap_hwmod *oh)

{

	/* TODO: For now just handle OMAP4+ */

	if (cpu_is_omap24xx() || cpu_is_omap34xx())

		return 0;



	if (!oh)

		return -EINVAL;



	if (oh->_int_flags & _HWMOD_NO_MPU_PORT)

		return 0;



	if (oh->flags & HWMOD_NO_IDLEST)

		return 0;



	return omap4_cminst_wait_module_idle(oh->clkdm->prcm_partition,

					     oh->clkdm->cm_inst,

					     oh->clkdm->clkdm_offs,

					     oh->prcm.omap4.clkctrl_offs);

}



/**

 * _lookup_hardreset - fill register bit info for this hwmod/reset line

 * @oh: struct omap_hwmod *
@@ -1524,8 +1532,6 @@ static int _enable(struct omap_hwmod *oh) 
 */

static int _idle(struct omap_hwmod *oh)

{

	int ret;



	pr_debug("omap_hwmod: %s: idling\n", oh->name);



	if (oh->_state != _HWMOD_STATE_ENABLED) {
@@ -1537,11 +1543,9 @@ static int _idle(struct omap_hwmod *oh) 
	if (oh->class->sysc)

		_idle_sysc(oh);

	_del_initiator_dep(oh, mpu_oh);

	_disable_module(oh);

	ret = _wait_target_disable(oh);

	if (ret)

		pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",

			oh->name);



	_omap4_disable_module(oh);



	/*

	 * The module must be in idle mode before disabling any parents

	 * clocks. Otherwise, the parent clock might be disabled before
@@ -1642,11 +1646,7 @@ static int _shutdown(struct omap_hwmod *oh) 
	if (oh->_state == _HWMOD_STATE_ENABLED) {

		_del_initiator_dep(oh, mpu_oh);

		/* XXX what about the other system initiators here? dma, dsp */

		_disable_module(oh);

		ret = _wait_target_disable(oh);

		if (ret)

			pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",

				oh->name);

		_omap4_disable_module(oh);

		_disable_clocks(oh);

		if (oh->clkdm)

			clkdm_hwmod_disable(oh->clkdm, oh);

arch/arm/mach-omap2/voltagedomains3xxx_data.c

+34 −6
Original line number Diff line number Diff line
@@ -31,6 +31,14 @@ 
 * VDD data

 */



/* OMAP3-common voltagedomain data */



static struct voltagedomain omap3_voltdm_wkup = {

	.name = "wakeup",

};



/* 34xx/36xx voltagedomain data */



static const struct omap_vfsm_instance omap3_vdd1_vfsm = {

	.voltsetup_reg = OMAP3_PRM_VOLTSETUP1_OFFSET,

	.voltsetup_mask = OMAP3430_SETUP_TIME1_MASK,
@@ -63,10 +71,6 @@ static struct voltagedomain omap3_voltdm_core = { 
	.vp = &omap3_vp_core,

};



static struct voltagedomain omap3_voltdm_wkup = {

	.name = "wakeup",

};



static struct voltagedomain *voltagedomains_omap3[] __initdata = {

	&omap3_voltdm_mpu,

	&omap3_voltdm_core,
@@ -74,11 +78,30 @@ static struct voltagedomain *voltagedomains_omap3[] __initdata = { 
	NULL,

};



/* AM35xx voltagedomain data */



static struct voltagedomain am35xx_voltdm_mpu = {

	.name = "mpu_iva",

};



static struct voltagedomain am35xx_voltdm_core = {

	.name = "core",

};



static struct voltagedomain *voltagedomains_am35xx[] __initdata = {

	&am35xx_voltdm_mpu,

	&am35xx_voltdm_core,

	&omap3_voltdm_wkup,

	NULL,

};





static const char *sys_clk_name __initdata = "sys_ck";



void __init omap3xxx_voltagedomains_init(void)

{

	struct voltagedomain *voltdm;

	struct voltagedomain **voltdms;

	int i;



	/*
@@ -93,8 +116,13 @@ void __init omap3xxx_voltagedomains_init(void) 
		omap3_voltdm_core.volt_data = omap34xx_vddcore_volt_data;

	}



	for (i = 0; voltdm = voltagedomains_omap3[i], voltdm; i++)

	if (cpu_is_omap3517() || cpu_is_omap3505())

		voltdms = voltagedomains_am35xx;

	else

		voltdms = voltagedomains_omap3;



	for (i = 0; voltdm = voltdms[i], voltdm; i++)

		voltdm->sys_clk.name = sys_clk_name;



	voltdm_init(voltagedomains_omap3);

	voltdm_init(voltdms);

};