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Commit bcb8a0d6 authored by Ben Dooks's avatar Ben Dooks
Browse files

[ARM] S3C: Merge next-s3c64xx-dma2 into for-rmk-devel 

Merge branch 'next-s3c64xx-dma2' into for-rmk-devel

Conflicts:

	arch/arm/plat-s3c64xx/Makefile
parents 543899f6 0b13406a

arch/arm/include/asm/hardware/pl080.h

0 → 100644
+138 −0
Original line number Diff line number Diff line 
/* arch/arm/include/asm/hardware/pl080.h

 *

 * Copyright 2008 Openmoko, Inc.

 * Copyright 2008 Simtec Electronics

 *      http://armlinux.simtec.co.uk/

 *      Ben Dooks <ben@simtec.co.uk>

 *

 * ARM PrimeCell PL080 DMA controller

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

*/



/* Note, there are some Samsung updates to this controller block which

 * make it not entierly compatible with the PL080 specification from

 * ARM. When in doubt, check the Samsung documentation first.

 *

 * The Samsung defines are PL080S, and add an extra controll register,

 * the ability to move more than 2^11 counts of data and some extra

 * OneNAND features.

*/



#define PL080_INT_STATUS			(0x00)

#define PL080_TC_STATUS				(0x04)

#define PL080_TC_CLEAR				(0x08)

#define PL080_ERR_STATUS			(0x0C)

#define PL080_ERR_CLEAR				(0x10)

#define PL080_RAW_TC_STATUS			(0x14)

#define PL080_RAW_ERR_STATUS			(0x18)

#define PL080_EN_CHAN				(0x1c)

#define PL080_SOFT_BREQ				(0x20)

#define PL080_SOFT_SREQ				(0x24)

#define PL080_SOFT_LBREQ			(0x28)

#define PL080_SOFT_LSREQ			(0x2C)



#define PL080_CONFIG				(0x30)

#define PL080_CONFIG_M2_BE			(1 << 2)

#define PL080_CONFIG_M1_BE			(1 << 1)

#define PL080_CONFIG_ENABLE			(1 << 0)



#define PL080_SYNC				(0x34)



/* Per channel configuration registers */



#define PL008_Cx_STRIDE				(0x20)

#define PL080_Cx_BASE(x)			((0x100 + (x * 0x20)))

#define PL080_Cx_SRC_ADDR(x)			((0x100 + (x * 0x20)))

#define PL080_Cx_DST_ADDR(x)			((0x104 + (x * 0x20)))

#define PL080_Cx_LLI(x)				((0x108 + (x * 0x20)))

#define PL080_Cx_CONTROL(x)			((0x10C + (x * 0x20)))

#define PL080_Cx_CONFIG(x)			((0x110 + (x * 0x20)))

#define PL080S_Cx_CONTROL2(x)			((0x110 + (x * 0x20)))

#define PL080S_Cx_CONFIG(x)			((0x114 + (x * 0x20)))



#define PL080_CH_SRC_ADDR			(0x00)

#define PL080_CH_DST_ADDR			(0x04)

#define PL080_CH_LLI				(0x08)

#define PL080_CH_CONTROL			(0x0C)

#define PL080_CH_CONFIG				(0x10)

#define PL080S_CH_CONTROL2			(0x10)

#define PL080S_CH_CONFIG			(0x14)



#define PL080_LLI_ADDR_MASK			(0x3fffffff << 2)

#define PL080_LLI_ADDR_SHIFT			(2)

#define PL080_LLI_LM_AHB2			(1 << 0)



#define PL080_CONTROL_TC_IRQ_EN			(1 << 31)

#define PL080_CONTROL_PROT_MASK			(0x7 << 28)

#define PL080_CONTROL_PROT_SHIFT		(28)

#define PL080_CONTROL_PROT_SYS			(1 << 28)

#define PL080_CONTROL_DST_INCR			(1 << 27)

#define PL080_CONTROL_SRC_INCR			(1 << 26)

#define PL080_CONTROL_DST_AHB2			(1 << 25)

#define PL080_CONTROL_SRC_AHB2			(1 << 24)

#define PL080_CONTROL_DWIDTH_MASK		(0x7 << 21)

#define PL080_CONTROL_DWIDTH_SHIFT		(21)

#define PL080_CONTROL_SWIDTH_MASK		(0x7 << 18)

#define PL080_CONTROL_SWIDTH_SHIFT		(18)

#define PL080_CONTROL_DB_SIZE_MASK		(0x7 << 15)

#define PL080_CONTROL_DB_SIZE_SHIFT		(15)

#define PL080_CONTROL_SB_SIZE_MASK		(0x7 << 12)

#define PL080_CONTROL_SB_SIZE_SHIFT		(12)

#define PL080_CONTROL_TRANSFER_SIZE_MASK	(0xfff << 0)

#define PL080_CONTROL_TRANSFER_SIZE_SHIFT	(0)



#define PL080_BSIZE_1				(0x0)

#define PL080_BSIZE_4				(0x1)

#define PL080_BSIZE_8				(0x2)

#define PL080_BSIZE_16				(0x3)

#define PL080_BSIZE_32				(0x4)

#define PL080_BSIZE_64				(0x5)

#define PL080_BSIZE_128				(0x6)

#define PL080_BSIZE_256				(0x7)



#define PL080_WIDTH_8BIT			(0x0)

#define PL080_WIDTH_16BIT			(0x1)

#define PL080_WIDTH_32BIT			(0x2)



#define PL080_CONFIG_HALT			(1 << 18)

#define PL080_CONFIG_ACTIVE			(1 << 17)  /* RO */

#define PL080_CONFIG_LOCK			(1 << 16)

#define PL080_CONFIG_TC_IRQ_MASK		(1 << 15)

#define PL080_CONFIG_ERR_IRQ_MASK		(1 << 14)

#define PL080_CONFIG_FLOW_CONTROL_MASK		(0x7 << 11)

#define PL080_CONFIG_FLOW_CONTROL_SHIFT		(11)

#define PL080_CONFIG_DST_SEL_MASK		(0xf << 6)

#define PL080_CONFIG_DST_SEL_SHIFT		(6)

#define PL080_CONFIG_SRC_SEL_MASK		(0xf << 1)

#define PL080_CONFIG_SRC_SEL_SHIFT		(1)

#define PL080_CONFIG_ENABLE			(1 << 0)



#define PL080_FLOW_MEM2MEM			(0x0)

#define PL080_FLOW_MEM2PER			(0x1)

#define PL080_FLOW_PER2MEM			(0x2)

#define PL080_FLOW_SRC2DST			(0x3)

#define PL080_FLOW_SRC2DST_DST			(0x4)

#define PL080_FLOW_MEM2PER_PER			(0x5)

#define PL080_FLOW_PER2MEM_PER			(0x6)

#define PL080_FLOW_SRC2DST_SRC			(0x7)



/* DMA linked list chain structure */



struct pl080_lli {

	u32	src_addr;

	u32	dst_addr;

	u32	next_lli;

	u32	control0;

};



struct pl080s_lli {

	u32	src_addr;

	u32	dst_addr;

	u32	next_lli;

	u32	control0;

	u32	control1;

};

arch/arm/mach-s3c2410/dma.c

+3 −1
Original line number Diff line number Diff line
@@ -17,14 +17,16 @@ 
#include <linux/sysdev.h>

#include <linux/serial_core.h>



#include <mach/map.h>

#include <mach/dma.h>



#include <plat/cpu.h>

#include <plat/dma.h>

#include <plat/dma-plat.h>



#include <plat/regs-serial.h>

#include <mach/regs-gpio.h>

#include <plat/regs-ac97.h>

#include <plat/regs-dma.h>

#include <mach/regs-mem.h>

#include <mach/regs-lcd.h>

#include <mach/regs-sdi.h>

arch/arm/mach-s3c2410/include/mach/dma.h

+7 −258
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@ 
 * Copyright (C) 2003,2004,2006 Simtec Electronics

 *	Ben Dooks <ben@simtec.co.uk>

 *

 * Samsung S3C241XX DMA support

 * Samsung S3C24XX DMA support

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as
@@ -13,8 +13,8 @@ 
#ifndef __ASM_ARCH_DMA_H

#define __ASM_ARCH_DMA_H __FILE__



#include <plat/dma.h>

#include <linux/sysdev.h>

#include <mach/hardware.h>



#define MAX_DMA_TRANSFER_SIZE   0x100000 /* Data Unit is half word  */
@@ -55,9 +55,9 @@ enum dma_ch { 


/* we have 4 dma channels */

#ifndef CONFIG_CPU_S3C2443

#define S3C2410_DMA_CHANNELS		(4)

#define S3C_DMA_CHANNELS		(4)

#else

#define S3C2410_DMA_CHANNELS		(6)

#define S3C_DMA_CHANNELS		(6)

#endif



/* types */
@@ -68,7 +68,6 @@ enum s3c2410_dma_state { 
	S3C2410_DMA_PAUSED

};





/* enum s3c2410_dma_loadst

 *

 * This represents the state of the DMA engine, wrt to the loaded / running
@@ -104,32 +103,6 @@ enum s3c2410_dma_loadst { 
	S3C2410_DMALOAD_1LOADED_1RUNNING,

};



enum s3c2410_dma_buffresult {

	S3C2410_RES_OK,

	S3C2410_RES_ERR,

	S3C2410_RES_ABORT

};



enum s3c2410_dmasrc {

	S3C2410_DMASRC_HW,		/* source is memory */

	S3C2410_DMASRC_MEM		/* source is hardware */

};



/* enum s3c2410_chan_op

 *

 * operation codes passed to the DMA code by the user, and also used

 * to inform the current channel owner of any changes to the system state

*/



enum s3c2410_chan_op {

	S3C2410_DMAOP_START,

	S3C2410_DMAOP_STOP,

	S3C2410_DMAOP_PAUSE,

	S3C2410_DMAOP_RESUME,

	S3C2410_DMAOP_FLUSH,

	S3C2410_DMAOP_TIMEOUT,		/* internal signal to handler */

	S3C2410_DMAOP_STARTED,		/* indicate channel started */

};



/* flags */
@@ -139,17 +112,14 @@ enum s3c2410_chan_op { 


/* dma buffer */



struct s3c2410_dma_client {

	char                *name;

};

struct s3c2410_dma_buf;



/* s3c2410_dma_buf_s

/* s3c2410_dma_buf

 *

 * internally used buffer structure to describe a queued or running

 * buffer.

*/



struct s3c2410_dma_buf;

struct s3c2410_dma_buf {

	struct s3c2410_dma_buf	*next;

	int			 magic;		/* magic */
@@ -161,20 +131,6 @@ struct s3c2410_dma_buf { 


/* [1] is this updated for both recv/send modes? */



struct s3c2410_dma_chan;



/* s3c2410_dma_cbfn_t

 *

 * buffer callback routine type

*/



typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *,

				   void *buf, int size,

				   enum s3c2410_dma_buffresult result);



typedef int  (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,

				   enum s3c2410_chan_op );



struct s3c2410_dma_stats {

	unsigned long		loads;

	unsigned long		timeout_longest;
@@ -206,10 +162,10 @@ struct s3c2410_dma_chan { 


	/* channel configuration */

	enum s3c2410_dmasrc	 source;

	enum dma_ch		 req_ch;

	unsigned long		 dev_addr;

	unsigned long		 load_timeout;

	unsigned int		 flags;		/* channel flags */

	unsigned int		 hw_cfg;	/* last hw config */



	struct s3c24xx_dma_map	*map;		/* channel hw maps */
@@ -236,213 +192,6 @@ struct s3c2410_dma_chan { 
	struct sys_device	dev;

};



/* the currently allocated channel information */

extern struct s3c2410_dma_chan s3c2410_chans[];



/* note, we don't really use dma_device_t at the moment */

typedef unsigned long dma_device_t;



/* functions --------------------------------------------------------------- */



/* s3c2410_dma_request

 *

 * request a dma channel exclusivley

*/



extern int s3c2410_dma_request(unsigned int channel,

			       struct s3c2410_dma_client *, void *dev);





/* s3c2410_dma_ctrl

 *

 * change the state of the dma channel

*/



extern int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op);



/* s3c2410_dma_setflags

 *

 * set the channel's flags to a given state

*/



extern int s3c2410_dma_setflags(unsigned int channel,

				unsigned int flags);



/* s3c2410_dma_free

 *

 * free the dma channel (will also abort any outstanding operations)

*/



extern int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *);



/* s3c2410_dma_enqueue

 *

 * place the given buffer onto the queue of operations for the channel.

 * The buffer must be allocated from dma coherent memory, or the Dcache/WB

 * drained before the buffer is given to the DMA system.

*/



extern int s3c2410_dma_enqueue(unsigned int channel, void *id,

			       dma_addr_t data, int size);



/* s3c2410_dma_config

 *

 * configure the dma channel

*/



extern int s3c2410_dma_config(unsigned int channel, int xferunit, int dcon);



/* s3c2410_dma_devconfig

 *

 * configure the device we're talking to

*/



extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source,

				 int hwcfg, unsigned long devaddr);



/* s3c2410_dma_getposition

 *

 * get the position that the dma transfer is currently at

*/



extern int s3c2410_dma_getposition(unsigned int channel,

				   dma_addr_t *src, dma_addr_t *dest);



extern int s3c2410_dma_set_opfn(unsigned int, s3c2410_dma_opfn_t rtn);

extern int s3c2410_dma_set_buffdone_fn(unsigned int, s3c2410_dma_cbfn_t rtn);



/* DMA Register definitions */



#define S3C2410_DMA_DISRC       (0x00)

#define S3C2410_DMA_DISRCC      (0x04)

#define S3C2410_DMA_DIDST       (0x08)

#define S3C2410_DMA_DIDSTC      (0x0C)

#define S3C2410_DMA_DCON        (0x10)

#define S3C2410_DMA_DSTAT       (0x14)

#define S3C2410_DMA_DCSRC       (0x18)

#define S3C2410_DMA_DCDST       (0x1C)

#define S3C2410_DMA_DMASKTRIG   (0x20)

#define S3C2412_DMA_DMAREQSEL	(0x24)

#define S3C2443_DMA_DMAREQSEL	(0x24)



#define S3C2410_DISRCC_INC	(1<<0)

#define S3C2410_DISRCC_APB	(1<<1)



#define S3C2410_DMASKTRIG_STOP   (1<<2)

#define S3C2410_DMASKTRIG_ON     (1<<1)

#define S3C2410_DMASKTRIG_SWTRIG (1<<0)



#define S3C2410_DCON_DEMAND     (0<<31)

#define S3C2410_DCON_HANDSHAKE  (1<<31)

#define S3C2410_DCON_SYNC_PCLK  (0<<30)

#define S3C2410_DCON_SYNC_HCLK  (1<<30)



#define S3C2410_DCON_INTREQ     (1<<29)



#define S3C2410_DCON_CH0_XDREQ0	(0<<24)

#define S3C2410_DCON_CH0_UART0	(1<<24)

#define S3C2410_DCON_CH0_SDI	(2<<24)

#define S3C2410_DCON_CH0_TIMER	(3<<24)

#define S3C2410_DCON_CH0_USBEP1	(4<<24)



#define S3C2410_DCON_CH1_XDREQ1	(0<<24)

#define S3C2410_DCON_CH1_UART1	(1<<24)

#define S3C2410_DCON_CH1_I2SSDI	(2<<24)

#define S3C2410_DCON_CH1_SPI	(3<<24)

#define S3C2410_DCON_CH1_USBEP2	(4<<24)



#define S3C2410_DCON_CH2_I2SSDO	(0<<24)

#define S3C2410_DCON_CH2_I2SSDI	(1<<24)

#define S3C2410_DCON_CH2_SDI	(2<<24)

#define S3C2410_DCON_CH2_TIMER	(3<<24)

#define S3C2410_DCON_CH2_USBEP3	(4<<24)



#define S3C2410_DCON_CH3_UART2	(0<<24)

#define S3C2410_DCON_CH3_SDI	(1<<24)

#define S3C2410_DCON_CH3_SPI	(2<<24)

#define S3C2410_DCON_CH3_TIMER	(3<<24)

#define S3C2410_DCON_CH3_USBEP4	(4<<24)



#define S3C2410_DCON_SRCSHIFT   (24)

#define S3C2410_DCON_SRCMASK	(7<<24)



#define S3C2410_DCON_BYTE       (0<<20)

#define S3C2410_DCON_HALFWORD   (1<<20)

#define S3C2410_DCON_WORD       (2<<20)



#define S3C2410_DCON_AUTORELOAD (0<<22)

#define S3C2410_DCON_NORELOAD   (1<<22)

#define S3C2410_DCON_HWTRIG     (1<<23)



#ifdef CONFIG_CPU_S3C2440

#define S3C2440_DIDSTC_CHKINT	(1<<2)



#define S3C2440_DCON_CH0_I2SSDO	(5<<24)

#define S3C2440_DCON_CH0_PCMIN	(6<<24)



#define S3C2440_DCON_CH1_PCMOUT	(5<<24)

#define S3C2440_DCON_CH1_SDI	(6<<24)



#define S3C2440_DCON_CH2_PCMIN	(5<<24)

#define S3C2440_DCON_CH2_MICIN	(6<<24)



#define S3C2440_DCON_CH3_MICIN	(5<<24)

#define S3C2440_DCON_CH3_PCMOUT	(6<<24)

#endif



#ifdef CONFIG_CPU_S3C2412



#define S3C2412_DMAREQSEL_SRC(x)	((x)<<1)



#define S3C2412_DMAREQSEL_HW		(1)



#define S3C2412_DMAREQSEL_SPI0TX	S3C2412_DMAREQSEL_SRC(0)

#define S3C2412_DMAREQSEL_SPI0RX	S3C2412_DMAREQSEL_SRC(1)

#define S3C2412_DMAREQSEL_SPI1TX	S3C2412_DMAREQSEL_SRC(2)

#define S3C2412_DMAREQSEL_SPI1RX	S3C2412_DMAREQSEL_SRC(3)

#define S3C2412_DMAREQSEL_I2STX		S3C2412_DMAREQSEL_SRC(4)

#define S3C2412_DMAREQSEL_I2SRX		S3C2412_DMAREQSEL_SRC(5)

#define S3C2412_DMAREQSEL_TIMER		S3C2412_DMAREQSEL_SRC(9)

#define S3C2412_DMAREQSEL_SDI		S3C2412_DMAREQSEL_SRC(10)

#define S3C2412_DMAREQSEL_USBEP1	S3C2412_DMAREQSEL_SRC(13)

#define S3C2412_DMAREQSEL_USBEP2	S3C2412_DMAREQSEL_SRC(14)

#define S3C2412_DMAREQSEL_USBEP3	S3C2412_DMAREQSEL_SRC(15)

#define S3C2412_DMAREQSEL_USBEP4	S3C2412_DMAREQSEL_SRC(16)

#define S3C2412_DMAREQSEL_XDREQ0	S3C2412_DMAREQSEL_SRC(17)

#define S3C2412_DMAREQSEL_XDREQ1	S3C2412_DMAREQSEL_SRC(18)

#define S3C2412_DMAREQSEL_UART0_0	S3C2412_DMAREQSEL_SRC(19)

#define S3C2412_DMAREQSEL_UART0_1	S3C2412_DMAREQSEL_SRC(20)

#define S3C2412_DMAREQSEL_UART1_0	S3C2412_DMAREQSEL_SRC(21)

#define S3C2412_DMAREQSEL_UART1_1	S3C2412_DMAREQSEL_SRC(22)

#define S3C2412_DMAREQSEL_UART2_0	S3C2412_DMAREQSEL_SRC(23)

#define S3C2412_DMAREQSEL_UART2_1	S3C2412_DMAREQSEL_SRC(24)



#endif



#define S3C2443_DMAREQSEL_SRC(x)	((x)<<1)



#define S3C2443_DMAREQSEL_HW		(1)



#define S3C2443_DMAREQSEL_SPI0TX	S3C2443_DMAREQSEL_SRC(0)

#define S3C2443_DMAREQSEL_SPI0RX	S3C2443_DMAREQSEL_SRC(1)

#define S3C2443_DMAREQSEL_SPI1TX	S3C2443_DMAREQSEL_SRC(2)

#define S3C2443_DMAREQSEL_SPI1RX	S3C2443_DMAREQSEL_SRC(3)

#define S3C2443_DMAREQSEL_I2STX		S3C2443_DMAREQSEL_SRC(4)

#define S3C2443_DMAREQSEL_I2SRX		S3C2443_DMAREQSEL_SRC(5)

#define S3C2443_DMAREQSEL_TIMER		S3C2443_DMAREQSEL_SRC(9)

#define S3C2443_DMAREQSEL_SDI		S3C2443_DMAREQSEL_SRC(10)

#define S3C2443_DMAREQSEL_XDREQ0	S3C2443_DMAREQSEL_SRC(17)

#define S3C2443_DMAREQSEL_XDREQ1	S3C2443_DMAREQSEL_SRC(18)

#define S3C2443_DMAREQSEL_UART0_0	S3C2443_DMAREQSEL_SRC(19)

#define S3C2443_DMAREQSEL_UART0_1	S3C2443_DMAREQSEL_SRC(20)

#define S3C2443_DMAREQSEL_UART1_0	S3C2443_DMAREQSEL_SRC(21)

#define S3C2443_DMAREQSEL_UART1_1	S3C2443_DMAREQSEL_SRC(22)

#define S3C2443_DMAREQSEL_UART2_0	S3C2443_DMAREQSEL_SRC(23)

#define S3C2443_DMAREQSEL_UART2_1	S3C2443_DMAREQSEL_SRC(24)

#define S3C2443_DMAREQSEL_UART3_0	S3C2443_DMAREQSEL_SRC(25)

#define S3C2443_DMAREQSEL_UART3_1	S3C2443_DMAREQSEL_SRC(26)

#define S3C2443_DMAREQSEL_PCMOUT	S3C2443_DMAREQSEL_SRC(27)

#define S3C2443_DMAREQSEL_PCMIN 	S3C2443_DMAREQSEL_SRC(28)

#define S3C2443_DMAREQSEL_MICIN		S3C2443_DMAREQSEL_SRC(29)



#endif /* __ASM_ARCH_DMA_H */

arch/arm/mach-s3c2412/dma.c

+2 −1
Original line number Diff line number Diff line
@@ -20,12 +20,13 @@ 


#include <mach/dma.h>



#include <plat/dma.h>

#include <plat/dma-plat.h>

#include <plat/cpu.h>



#include <plat/regs-serial.h>

#include <mach/regs-gpio.h>

#include <plat/regs-ac97.h>

#include <plat/regs-dma.h>

#include <mach/regs-mem.h>

#include <mach/regs-lcd.h>

#include <mach/regs-sdi.h>

arch/arm/mach-s3c2440/dma.c

+3 −1
Original line number Diff line number Diff line
@@ -17,14 +17,16 @@ 
#include <linux/sysdev.h>

#include <linux/serial_core.h>



#include <mach/map.h>

#include <mach/dma.h>



#include <plat/dma.h>

#include <plat/dma-plat.h>

#include <plat/cpu.h>



#include <plat/regs-serial.h>

#include <mach/regs-gpio.h>

#include <plat/regs-ac97.h>

#include <plat/regs-dma.h>

#include <mach/regs-mem.h>

#include <mach/regs-lcd.h>

#include <mach/regs-sdi.h>