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Commit bc6b92f8 authored by Sonic Zhang's avatar Sonic Zhang Committed by Mike Frysinger
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Blackfin: don't attempt to flush on-chip L1 SRAM regions 



Since the on-chip L1 regions are not cacheable, there is no point in
trying to flush/invalidate them.  Plus, older Blackfin parts like to
trigger an exception (like BF533-0.3).

Signed-off-by: default avatarSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: default avatarMike Frysinger <vapier@gentoo.org>
parent 73ecfcf9

arch/blackfin/include/asm/cacheflush.h

+18 −5
Original line number Diff line number Diff line
@@ -39,7 +39,12 @@ extern void blackfin_invalidate_entire_icache(void); 


static inline void flush_icache_range(unsigned start, unsigned end)

{

#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)

#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK)

	if (end <= physical_mem_end)

		blackfin_dcache_flush_range(start, end);

#endif

#if defined(CONFIG_BFIN_L2_WRITEBACK)

	if (start >= L2_START && end <= L2_START + L2_LENGTH)

		blackfin_dcache_flush_range(start, end);

#endif
@@ -52,9 +57,17 @@ static inline void flush_icache_range(unsigned start, unsigned end) 
	 * the pipeline.

	 */

	SSYNC();

#if defined(CONFIG_BFIN_ICACHE)

#if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE)

	if (end <= physical_mem_end) {

		blackfin_icache_flush_range(start, end);

		flush_icache_range_others(start, end);

	}

#endif

#if defined(CONFIG_BFIN_L2_ICACHEABLE)

	if (start >= L2_START && end <= L2_START + L2_LENGTH) {

		blackfin_icache_flush_range(start, end);

		flush_icache_range_others(start, end);

	}

#endif

}