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Commit bc407b4f authored by Jordan Crouse's avatar Jordan Crouse
Browse files

msm: kgsl: Move the logic for the IOMMU sync workaround 



As part of our effort to move more device specific configuration to
the device tree add qcom,quirk-iommu-sync to the device tree and
remove it from the device features.  We also know that the mutex must
be enforced globally so we can pull it out of the device specific
structure and streamline the usage slightly.

Change-Id: Ic0dedbadef6290dbc6d4e05372cd3014a4203e8a
Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
parent bfbfa771

arch/arm/boot/dts/qcom/msm8996-v2.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -394,6 +394,7 @@ 


	/* Quirks */

	qcom,gpu-quirk-two-pass-use-wfi;

	qcom,gpu-quirk-iommu-sync;



	/* Power levels */

	qcom,gpu-pwrlevels {

drivers/gpu/msm/adreno-gpulist.h

+1 −2
Original line number Diff line number Diff line
@@ -139,7 +139,6 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.major = 3,

		.minor = 0,

		.patchid = 0,

		.features = ADRENO_SYNC_SMMU_PC,

		.pm4fw_name = "a530v1_pm4.fw",

		.pfpfw_name = "a530v1_pfp.fw",

		.gpudev = &adreno_a5xx_gpudev,
@@ -154,7 +153,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.minor = 0,

		.patchid = 1,

		.features = ADRENO_GPMU | ADRENO_SPTP_PC | ADRENO_LM |

			ADRENO_PREEMPTION | ADRENO_SYNC_SMMU_PC | ADRENO_64BIT |

			ADRENO_PREEMPTION | ADRENO_64BIT |

			ADRENO_CONTENT_PROTECTION,

		.pm4fw_name = "a530_pm4.fw",

		.pfpfw_name = "a530_pfp.fw",

drivers/gpu/msm/adreno.c

+30 −29
Original line number Diff line number Diff line
@@ -944,6 +944,7 @@ static struct { 
	const char *prop;

} adreno_quirks[] = {

	 { ADRENO_QUIRK_TWO_PASS_USE_WFI, "qcom,gpu-quirk-two-pass-use-wfi" },

	 { ADRENO_QUIRK_IOMMU_SYNC, "qcom,gpu-quirk-iommu-sync" },

};



static int adreno_of_get_pdata(struct adreno_device *adreno_dev)
@@ -2729,15 +2730,11 @@ static void adreno_pwrlevel_change_settings(struct kgsl_device *device, 


static void adreno_iommu_sync(struct kgsl_device *device, bool sync)

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	struct scm_desc desc = {0};

	int ret;



	if (!ADRENO_FEATURE(adreno_dev, ADRENO_SYNC_SMMU_PC))

		return;



	if (sync == true) {

		mutex_lock(&device->mutex_mmu_sync);

		mutex_lock(&kgsl_mmu_sync);

		desc.args[0] = true;

		desc.arginfo = SCM_ARGS(1);

		ret = scm_call2_atomic(SCM_SIP_FNID(SCM_SVC_PWR, 0x8), &desc);
@@ -2748,7 +2745,7 @@ static void adreno_iommu_sync(struct kgsl_device *device, bool sync) 
		desc.args[0] = false;

		desc.arginfo = SCM_ARGS(1);

		scm_call2_atomic(SCM_SIP_FNID(SCM_SVC_PWR, 0x8), &desc);

		mutex_unlock(&device->mutex_mmu_sync);

		mutex_unlock(&kgsl_mmu_sync);

	}

}
@@ -2759,9 +2756,17 @@ static void adreno_regulator_disable_poll(struct kgsl_device *device) 
	unsigned long wait_time;

	int i, rail_on;



	if (ADRENO_FEATURE(adreno_dev, ADRENO_SYNC_SMMU_PC)) {

	/* Fast path - hopefully we don't need this quirk */

	if (!ADRENO_QUIRK(adreno_dev, ADRENO_QUIRK_IOMMU_SYNC)) {

		for (i = KGSL_MAX_REGULATORS - 1; i >= 0; i--)

			if (pwr->gpu_reg[i] != NULL)

				regulator_disable(pwr->gpu_reg[i]);

		return;

	}



	adreno_iommu_sync(device, true);

		/* Turn off CX and then GX as recommened by HW team */



	/* Turn off CX and then GX as recommended by HW team */

	for (i = 0; i <= KGSL_MAX_REGULATORS - 1; i++) {

		if (pwr->gpu_reg[i] == NULL)

			continue;
@@ -2779,12 +2784,8 @@ static void adreno_regulator_disable_poll(struct kgsl_device *device) 
			KGSL_CORE_ERR("%s regulator on after 200ms\n",

				pwr->gpu_reg_name[i]);

	}



	adreno_iommu_sync(device, false);

	} else {

		for (i = KGSL_MAX_REGULATORS - 1; i >= 0; i--)

			if (pwr->gpu_reg[i])

				regulator_disable(pwr->gpu_reg[i]);

	}

}



static const struct kgsl_functable adreno_functable = {

drivers/gpu/msm/adreno.h

+2 −2
Original line number Diff line number Diff line
@@ -108,8 +108,6 @@ 
#define ADRENO_LM BIT(8)

/* The core uses 64 bit GPU addresses */

#define ADRENO_64BIT BIT(9)

/* Sync between SMMU operations and power collapse */

#define ADRENO_SYNC_SMMU_PC BIT(10)



/*

 * Adreno GPU quirks - control bits for various workarounds
@@ -117,6 +115,8 @@ 


/* Set TWOPASSUSEWFI in PC_DBG_ECO_CNTL (5XX) */

#define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0)

/* Lock/unlock mutex to sync with the IOMMU */

#define ADRENO_QUIRK_IOMMU_SYNC BIT(1)



/* Flags to control command packet settings */

#define KGSL_CMD_FLAGS_NONE             0

drivers/gpu/msm/kgsl.c

+4 −0
Original line number Diff line number Diff line
@@ -68,6 +68,10 @@ module_param_named(mmutype, ksgl_mmu_type, charp, 0); 
MODULE_PARM_DESC(ksgl_mmu_type,

"Type of MMU to be used for graphics. Valid values are 'iommu' or 'nommu'");



/* Mutex used for the IOMMU sync quirk */

DEFINE_MUTEX(kgsl_mmu_sync);

EXPORT_SYMBOL(kgsl_mmu_sync);



struct kgsl_dma_buf_meta {

	struct dma_buf_attachment *attach;

	struct dma_buf *dmabuf;