Loading Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt +1 −0 Original line number Diff line number Diff line Loading @@ -79,6 +79,7 @@ Optional properties: - qcom,qdsp6v62-1-2: Boolean- Present if the qdsp version is v62 1.2 - qcom,mx-spike-wa: Boolean- Present if we need to assert QDSP6 I/O clamp, memory wordline clamp, and compiler memory clamp during MSS restart. - qcom,qdsp6v56-1-10: Boolean- Present if the qdsp version is v56 1.10 Example: qcom,mss@fc880000 { Loading arch/arm/boot/dts/qcom/msmtitanium-smp2p.dtsi +23 −0 Original line number Diff line number Diff line Loading @@ -158,6 +158,29 @@ gpios = <&smp2pgpio_smp2p_2_out 0 0>; }; /* ssr - inbound entry from mss. */ smp2pgpio_ssr_smp2p_1_in: qcom,smp2pgpio-ssr-smp2p-1-in { compatible = "qcom,smp2pgpio"; qcom,entry-name = "slave-kernel"; qcom,remote-pid = <1>; qcom,is-inbound; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; /* ssr - outbound entry to mss */ smp2pgpio_ssr_smp2p_1_out: qcom,smp2pgpio-ssr-smp2p-1-out { compatible = "qcom,smp2pgpio"; qcom,entry-name = "master-kernel"; qcom,remote-pid = <1>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; /* ssr - inbound entry from lpass. */ smp2pgpio_ssr_smp2p_2_in: qcom,smp2pgpio-ssr-smp2p-2-in { compatible = "qcom,smp2pgpio"; Loading arch/arm/boot/dts/qcom/msmtitanium.dtsi +46 −0 Original line number Diff line number Diff line Loading @@ -1702,6 +1702,52 @@ }; }; qcom,mss@4080000 { compatible = "qcom,pil-q6v55-mss"; reg = <0x04080000 0x100>, <0x0194f000 0x010>, <0x01950000 0x008>, <0x01951000 0x008>, <0x04020000 0x040>, <0x01871000 0x004>; reg-names = "qdsp6_base", "halt_q6", "halt_modem", "halt_nc", "rmb_base", "restart_reg"; interrupts = <0 24 1>; vdd_mss-supply = <&pmtitanium_s1>; vdd_cx-supply = <&pmtitanium_s2_level>; vdd_cx-voltage = <RPM_SMD_REGULATOR_LEVEL_TURBO>; vdd_mx-supply = <&pmtitanium_s7_level_ao>; vdd_mx-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>; vdd_pll-supply = <&pmtitanium_l7>; qcom,vdd_pll = <1800000>; clocks = <&clock_gcc clk_xo_pil_mss_clk>, <&clock_gcc clk_gcc_mss_cfg_ahb_clk>, <&clock_gcc clk_gcc_mss_q6_bimc_axi_clk>, <&clock_gcc clk_gcc_boot_rom_ahb_clk>; clock-names = "xo", "iface_clk", "bus_clk", "mem_clk"; qcom,proxy-clock-names = "xo"; qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk"; qcom,firmware-name = "modem"; qcom,pil-self-auth; qcom,sysmon-id = <0>; qcom,ssctl-instance-id = <0x12>; qcom,qdsp6v56-1-10; /* GPIO inputs from mss */ qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>; qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>; qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>; qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>; qcom,gpio-shutdown-ack = <&smp2pgpio_ssr_smp2p_1_in 7 0>; /* GPIO output to mss */ qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>; memory-region = <&modem_mem>; }; qcom,lpass@c200000 { compatible = "qcom,pil-tz-generic"; reg = <0xc200000 0x00100>; Loading drivers/soc/qcom/pil-q6v5.c +4 −1 Original line number Diff line number Diff line Loading @@ -420,7 +420,8 @@ static int __pil_q6v55_reset(struct pil_desc *pil) writel_relaxed(val, drv->reg_base + QDSP6SS_PWR_CTL); udelay(1); } } else if (drv->qdsp6v56_1_5 || drv->qdsp6v56_1_8) { } else if (drv->qdsp6v56_1_5 || drv->qdsp6v56_1_8 || drv->qdsp6v56_1_10) { /* Deassert QDSP6 compiler memory clamp */ val = readl_relaxed(drv->reg_base + QDSP6SS_PWR_CTL); val &= ~QDSP6v55_CLAMP_QMC_MEM; Loading Loading @@ -637,6 +638,8 @@ struct q6v5_data *pil_q6v5_init(struct platform_device *pdev) drv->qdsp6v56_1_8 = of_property_read_bool(pdev->dev.of_node, "qcom,qdsp6v56-1-8"); drv->qdsp6v56_1_10 = of_property_read_bool(pdev->dev.of_node, "qcom,qdsp6v56-1-10"); drv->qdsp6v56_1_8_inrush_current = of_property_read_bool( pdev->dev.of_node, Loading drivers/soc/qcom/pil-q6v5.h +1 −0 Original line number Diff line number Diff line Loading @@ -59,6 +59,7 @@ struct q6v5_data { bool qdsp6v56_1_5; bool qdsp6v56_1_8; bool qdsp6v56_1_8_inrush_current; bool qdsp6v56_1_10; bool qdsp6v61_1_1; bool qdsp6v62_1_2; bool non_elf_image; Loading Loading
Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt +1 −0 Original line number Diff line number Diff line Loading @@ -79,6 +79,7 @@ Optional properties: - qcom,qdsp6v62-1-2: Boolean- Present if the qdsp version is v62 1.2 - qcom,mx-spike-wa: Boolean- Present if we need to assert QDSP6 I/O clamp, memory wordline clamp, and compiler memory clamp during MSS restart. - qcom,qdsp6v56-1-10: Boolean- Present if the qdsp version is v56 1.10 Example: qcom,mss@fc880000 { Loading
arch/arm/boot/dts/qcom/msmtitanium-smp2p.dtsi +23 −0 Original line number Diff line number Diff line Loading @@ -158,6 +158,29 @@ gpios = <&smp2pgpio_smp2p_2_out 0 0>; }; /* ssr - inbound entry from mss. */ smp2pgpio_ssr_smp2p_1_in: qcom,smp2pgpio-ssr-smp2p-1-in { compatible = "qcom,smp2pgpio"; qcom,entry-name = "slave-kernel"; qcom,remote-pid = <1>; qcom,is-inbound; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; /* ssr - outbound entry to mss */ smp2pgpio_ssr_smp2p_1_out: qcom,smp2pgpio-ssr-smp2p-1-out { compatible = "qcom,smp2pgpio"; qcom,entry-name = "master-kernel"; qcom,remote-pid = <1>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; /* ssr - inbound entry from lpass. */ smp2pgpio_ssr_smp2p_2_in: qcom,smp2pgpio-ssr-smp2p-2-in { compatible = "qcom,smp2pgpio"; Loading
arch/arm/boot/dts/qcom/msmtitanium.dtsi +46 −0 Original line number Diff line number Diff line Loading @@ -1702,6 +1702,52 @@ }; }; qcom,mss@4080000 { compatible = "qcom,pil-q6v55-mss"; reg = <0x04080000 0x100>, <0x0194f000 0x010>, <0x01950000 0x008>, <0x01951000 0x008>, <0x04020000 0x040>, <0x01871000 0x004>; reg-names = "qdsp6_base", "halt_q6", "halt_modem", "halt_nc", "rmb_base", "restart_reg"; interrupts = <0 24 1>; vdd_mss-supply = <&pmtitanium_s1>; vdd_cx-supply = <&pmtitanium_s2_level>; vdd_cx-voltage = <RPM_SMD_REGULATOR_LEVEL_TURBO>; vdd_mx-supply = <&pmtitanium_s7_level_ao>; vdd_mx-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>; vdd_pll-supply = <&pmtitanium_l7>; qcom,vdd_pll = <1800000>; clocks = <&clock_gcc clk_xo_pil_mss_clk>, <&clock_gcc clk_gcc_mss_cfg_ahb_clk>, <&clock_gcc clk_gcc_mss_q6_bimc_axi_clk>, <&clock_gcc clk_gcc_boot_rom_ahb_clk>; clock-names = "xo", "iface_clk", "bus_clk", "mem_clk"; qcom,proxy-clock-names = "xo"; qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk"; qcom,firmware-name = "modem"; qcom,pil-self-auth; qcom,sysmon-id = <0>; qcom,ssctl-instance-id = <0x12>; qcom,qdsp6v56-1-10; /* GPIO inputs from mss */ qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>; qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>; qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>; qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>; qcom,gpio-shutdown-ack = <&smp2pgpio_ssr_smp2p_1_in 7 0>; /* GPIO output to mss */ qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>; memory-region = <&modem_mem>; }; qcom,lpass@c200000 { compatible = "qcom,pil-tz-generic"; reg = <0xc200000 0x00100>; Loading
drivers/soc/qcom/pil-q6v5.c +4 −1 Original line number Diff line number Diff line Loading @@ -420,7 +420,8 @@ static int __pil_q6v55_reset(struct pil_desc *pil) writel_relaxed(val, drv->reg_base + QDSP6SS_PWR_CTL); udelay(1); } } else if (drv->qdsp6v56_1_5 || drv->qdsp6v56_1_8) { } else if (drv->qdsp6v56_1_5 || drv->qdsp6v56_1_8 || drv->qdsp6v56_1_10) { /* Deassert QDSP6 compiler memory clamp */ val = readl_relaxed(drv->reg_base + QDSP6SS_PWR_CTL); val &= ~QDSP6v55_CLAMP_QMC_MEM; Loading Loading @@ -637,6 +638,8 @@ struct q6v5_data *pil_q6v5_init(struct platform_device *pdev) drv->qdsp6v56_1_8 = of_property_read_bool(pdev->dev.of_node, "qcom,qdsp6v56-1-8"); drv->qdsp6v56_1_10 = of_property_read_bool(pdev->dev.of_node, "qcom,qdsp6v56-1-10"); drv->qdsp6v56_1_8_inrush_current = of_property_read_bool( pdev->dev.of_node, Loading
drivers/soc/qcom/pil-q6v5.h +1 −0 Original line number Diff line number Diff line Loading @@ -59,6 +59,7 @@ struct q6v5_data { bool qdsp6v56_1_5; bool qdsp6v56_1_8; bool qdsp6v56_1_8_inrush_current; bool qdsp6v56_1_10; bool qdsp6v61_1_1; bool qdsp6v62_1_2; bool non_elf_image; Loading