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Commit bbffe435 authored by Bjorn Helgaas's avatar Bjorn Helgaas
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PCI: leave MEM and IO decoding disabled during 64-bit BAR sizing, too 

After 253d2e54, we disable MEM and IO decoding for most devices while we
size 32-bit BARs.  However, we restore the original COMMAND register before
we size the upper 32 bits of 64-bit BARs, so we can still cause a conflict.

This patch waits to restore the original COMMAND register until we're
completely finished sizing the BAR.

Reference: https://lkml.org/lkml/2007/8/25/154


Acked-by: default avatarJacob Pan <jacob.jun.pan@linux.intel.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent cfaf0251

drivers/pci/probe.c

+3 −3
Original line number Diff line number Diff line
@@ -152,9 +152,6 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 
	pci_read_config_dword(dev, pos, &sz);

	pci_write_config_dword(dev, pos, l);



	if (!dev->mmio_always_on)

		pci_write_config_word(dev, PCI_COMMAND, orig_cmd);



	/*

	 * All bits set in sz means the device isn't working properly.

	 * If the BAR isn't implemented, all bits must be 0.  If it's a
@@ -239,6 +236,9 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 
	}



 out:

	if (!dev->mmio_always_on)

		pci_write_config_word(dev, PCI_COMMAND, orig_cmd);



	return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;

 fail:

	res->flags = 0;