Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit bbf8906b authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/fifo: audit and version fifo channel classes 



The full object interfaces are about to be exposed to userspace, so we
need to check for any security-related issues and version the structs
to make it easier to handle any changes we may need in the future.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent a532da97

drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c

+4 −4
Original line number Diff line number Diff line
@@ -52,10 +52,10 @@ nv04_dmaobj_bind(struct nouveau_dmaobj *dmaobj, 


	if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {

		switch (nv_mclass(parent->parent)) {

		case NV03_CHANNEL_DMA_CLASS:

		case NV10_CHANNEL_DMA_CLASS:

		case NV17_CHANNEL_DMA_CLASS:

		case NV40_CHANNEL_DMA_CLASS:

		case NV03_CHANNEL_DMA:

		case NV10_CHANNEL_DMA:

		case NV17_CHANNEL_DMA:

		case NV40_CHANNEL_DMA:

			break;

		default:

			return -EINVAL;

drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c

+3 −4
Original line number Diff line number Diff line
@@ -48,10 +48,9 @@ nv50_dmaobj_bind(struct nouveau_dmaobj *dmaobj, 


	if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {

		switch (nv_mclass(parent->parent)) {

		case NV50_CHANNEL_DMA_CLASS:

		case NV84_CHANNEL_DMA_CLASS:

		case NV50_CHANNEL_IND_CLASS:

		case NV84_CHANNEL_IND_CLASS:

		case NV40_CHANNEL_DMA:

		case NV50_CHANNEL_GPFIFO:

		case G82_CHANNEL_GPFIFO:

		case NV50_DISP_MAST_CLASS:

		case NV84_DISP_MAST_CLASS:

		case NV94_DISP_MAST_CLASS:

drivers/gpu/drm/nouveau/core/engine/fifo/base.c

+2 −1
Original line number Diff line number Diff line
@@ -26,7 +26,8 @@ 
#include <core/object.h>

#include <core/handle.h>

#include <core/event.h>

#include <core/class.h>

#include <nvif/unpack.h>

#include <nvif/class.h>



#include <engine/dmaobj.h>

#include <engine/fifo.h>

drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c

+19 −9
Original line number Diff line number Diff line
@@ -22,8 +22,9 @@ 
 * Authors: Ben Skeggs

 */



#include <core/os.h>

#include <core/class.h>

#include <core/client.h>

#include <nvif/unpack.h>

#include <nvif/class.h>

#include <core/engctx.h>

#include <core/namedb.h>

#include <core/handle.h>
@@ -117,16 +118,23 @@ nv04_fifo_chan_ctor(struct nouveau_object *parent, 
		    struct nouveau_oclass *oclass, void *data, u32 size,

		    struct nouveau_object **pobject)

{

	union {

		struct nv03_channel_dma_v0 v0;

	} *args = data;

	struct nv04_fifo_priv *priv = (void *)engine;

	struct nv04_fifo_chan *chan;

	struct nv03_channel_dma_class *args = data;

	int ret;



	if (size < sizeof(*args))

		return -EINVAL;

	nv_ioctl(parent, "create channel dma size %d\n", size);

	if (nvif_unpack(args->v0, 0, 0, false)) {

		nv_ioctl(parent, "create channel dma vers %d pushbuf %08x "

				 "offset %016llx\n", args->v0.version,

			 args->v0.pushbuf, args->v0.offset);

	} else

		return ret;



	ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0x800000,

					  0x10000, args->pushbuf,

					  0x10000, args->v0.pushbuf,

					  (1ULL << NVDEV_ENGINE_DMAOBJ) |

					  (1ULL << NVDEV_ENGINE_SW) |

					  (1ULL << NVDEV_ENGINE_GR), &chan);
@@ -134,13 +142,15 @@ nv04_fifo_chan_ctor(struct nouveau_object *parent, 
	if (ret)

		return ret;



	args->v0.chid = chan->base.chid;



	nv_parent(chan)->object_attach = nv04_fifo_object_attach;

	nv_parent(chan)->object_detach = nv04_fifo_object_detach;

	nv_parent(chan)->context_attach = nv04_fifo_context_attach;

	chan->ramfc = chan->base.chid * 32;



	nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->offset);

	nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->offset);

	nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->v0.offset);

	nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->v0.offset);

	nv_wo32(priv->ramfc, chan->ramfc + 0x08, chan->base.pushgpu->addr >> 4);

	nv_wo32(priv->ramfc, chan->ramfc + 0x10,

			     NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
@@ -248,7 +258,7 @@ nv04_fifo_ofuncs = { 


static struct nouveau_oclass

nv04_fifo_sclass[] = {

	{ NV03_CHANNEL_DMA_CLASS, &nv04_fifo_ofuncs },

	{ NV03_CHANNEL_DMA, &nv04_fifo_ofuncs },

	{}

};

drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c

+19 −9
Original line number Diff line number Diff line
@@ -22,8 +22,9 @@ 
 * Authors: Ben Skeggs

 */



#include <core/os.h>

#include <core/class.h>

#include <core/client.h>

#include <nvif/unpack.h>

#include <nvif/class.h>

#include <core/engctx.h>

#include <core/ramht.h>
@@ -59,16 +60,23 @@ nv10_fifo_chan_ctor(struct nouveau_object *parent, 
		    struct nouveau_oclass *oclass, void *data, u32 size,

		    struct nouveau_object **pobject)

{

	union {

		struct nv03_channel_dma_v0 v0;

	} *args = data;

	struct nv04_fifo_priv *priv = (void *)engine;

	struct nv04_fifo_chan *chan;

	struct nv03_channel_dma_class *args = data;

	int ret;



	if (size < sizeof(*args))

		return -EINVAL;

	nv_ioctl(parent, "create channel dma size %d\n", size);

	if (nvif_unpack(args->v0, 0, 0, false)) {

		nv_ioctl(parent, "create channel dma vers %d pushbuf %08x "

				 "offset %016llx\n", args->v0.version,

			 args->v0.pushbuf, args->v0.offset);

	} else

		return ret;



	ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0x800000,

					  0x10000, args->pushbuf,

					  0x10000, args->v0.pushbuf,

					  (1ULL << NVDEV_ENGINE_DMAOBJ) |

					  (1ULL << NVDEV_ENGINE_SW) |

					  (1ULL << NVDEV_ENGINE_GR), &chan);
@@ -76,13 +84,15 @@ nv10_fifo_chan_ctor(struct nouveau_object *parent, 
	if (ret)

		return ret;



	args->v0.chid = chan->base.chid;



	nv_parent(chan)->object_attach = nv04_fifo_object_attach;

	nv_parent(chan)->object_detach = nv04_fifo_object_detach;

	nv_parent(chan)->context_attach = nv04_fifo_context_attach;

	chan->ramfc = chan->base.chid * 32;



	nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->offset);

	nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->offset);

	nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->v0.offset);

	nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->v0.offset);

	nv_wo32(priv->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4);

	nv_wo32(priv->ramfc, chan->ramfc + 0x14,

			     NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
@@ -106,7 +116,7 @@ nv10_fifo_ofuncs = { 


static struct nouveau_oclass

nv10_fifo_sclass[] = {

	{ NV10_CHANNEL_DMA_CLASS, &nv10_fifo_ofuncs },

	{ NV10_CHANNEL_DMA, &nv10_fifo_ofuncs },

	{}

};