Merge "ARM: dts: msm: update PCIe nodes to be compatible on MDM9640" (bb713479) · Commits · e / devices / android_kernel_xiaomi_markw

arch/arm/boot/dts/qcom/mdm9640-pinctrl.dtsi

+2 −2

Original line number	Diff line number	Diff line
		@@ -261,7 +261,7 @@
		pcie0_clkreq_default: pcie0_clkreq_default {
		mux {
		pins = "gpio64";
		function = "pci_e";
		function = "pcie_clkreq";
		};

		config {
		@@ -295,7 +295,7 @@
		config {
		pins = "gpio65";
		drive-strength = <2>;
		bias-pull-up;
		bias-disable; /* NO pull */
		};
		};
		};

arch/arm/boot/dts/qcom/mdm9640.dtsi

+70 −15

Original line number	Diff line number	Diff line
		@@ -487,29 +487,80 @@
		reg-names = "parf", "phy", "dm_core", "elbi",
		"conf", "io", "bars";

		#address-cells = <0>;
		#address-cells = <3>;
		#size-cells = <2>;
		ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
		<0x02000000 0x0 0x40300000 0x40300000 0x0 0xd00000>;
		interrupt-parent = <&pcie0>;
		interrupts = <0 1 2 3 4 5 6 7 8 9 10 11>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0xffffffff>;
		interrupt-map = <0 &intc 0 49 0
		1 &intc 0 50 0
		2 &intc 0 51 0
		3 &intc 0 52 0
		4 &intc 0 53 0
		5 &intc 0 54 0
		6 &intc 0 55 0
		7 &intc 0 56 0
		8 &intc 0 57 0
		9 &intc 0 58 0
		10 &intc 0 59 0
		11 &intc 0 60 0>;
		interrupt-map-mask = <0 0 0 0xffffffff>;
		interrupt-map = <0 0 0 0 &intc 0 49 0
		0 0 0 1 &intc 0 50 0
		0 0 0 2 &intc 0 51 0
		0 0 0 3 &intc 0 52 0
		0 0 0 4 &intc 0 53 0
		0 0 0 5 &intc 0 54 0
		0 0 0 6 &intc 0 55 0
		0 0 0 7 &intc 0 56 0
		0 0 0 8 &intc 0 57 0
		0 0 0 9 &intc 0 58 0
		0 0 0 10 &intc 0 59 0
		0 0 0 11 &intc 0 60 0>;

		interrupt-names = "int_msi", "int_a", "int_b", "int_c", "int_d",
		"int_pls_pme", "int_pme_legacy", "int_pls_err",
		"int_aer_legacy", "int_pls_link_up",
		"int_pls_link_down", "int_bridge_flush_n";

		qcom,phy-sequence = <0x604 0x03 0x00
		0x048 0x08 0x00
		0x0ac 0x82 0x00
		0x10c 0x03 0x00
		0x100 0xd5 0x00
		0x104 0xaa 0x00
		0x108 0x4d 0x00
		0x09c 0x03 0x00
		0x090 0x06 0x00
		0x094 0x1a 0x00
		0x114 0x7c 0x00
		0x034 0x1f 0x00
		0x038 0x12 0x00
		0x03c 0x0f 0x00
		0x024 0x01 0x00
		0x00c 0x0f 0x00
		0x010 0x0f 0x00
		0x014 0x46 0x00
		0x400 0xf4 0x00
		0x408 0x2c 0x00
		0x004 0xe1 0x00
		0x04c 0x91 0x00
		0x050 0x07 0x00
		0x0e0 0x20 0x00
		0x0e8 0x77 0x00
		0x0f0 0x15 0x00
		0x268 0x03 0x00
		0x414 0x09 0x00
		0x418 0x04 0x00
		0x41c 0x49 0x00
		0x4a8 0xff 0x00
		0x4ac 0x1f 0x00
		0x4b0 0xff 0x00
		0x4b4 0x00 0x00
		0x4bc 0x1e 0x00
		0x4f0 0x67 0x00
		0x4f4 0x80 0x00
		0x4f8 0x40 0x00
		0x500 0xb0 0x00
		0x504 0x06 0x00
		0x110 0x10 0x00
		0x648 0x10 0x00
		0x650 0xa3 0x00
		0x654 0x4b 0x00
		0x64c 0x4d 0x00
		0x600 0x00 0x00
		0x608 0x03 0x00>;

		pinctrl-names = "default";
		pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default
		&pcie0_wake_default>;
		@@ -527,6 +578,10 @@

		qcom,ep-wakeirq;

		linux,pci-domain = <0>;

		qcom,pcie-phy-ver = <0x90>;

		qcom,ep-latency = <10>;

		qcom,msm-bus,name = "pcie0";
		@@ -551,7 +606,7 @@
		"pcie_0_slv_axi_clk", "pcie_0_ldo",
		"pcie_0_phy_reset";

		max-clock-frequency-hz = <125000000>, <0>, <1000000>,
		max-clock-frequency-hz = <125000000>, <0>, <1010000>,
		<0>, <0>, <0>, <0>, <0>, <0>;
		};

drivers/pci/host/pci-msm.c

+29 −1

Original line number	Diff line number	Diff line
		@@ -53,10 +53,25 @@
		#define PCIE20_PARF_DBI_BASE_ADDR 0x350
		#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x358

		#define PCIE_N_PCS_STATUS(n, m) (PCS_PORT(n, m) + 0x174)

		#define TX_BASE 0x200
		#define RX_BASE 0x400
		#define PCS_BASE 0x800
		#define PCS_MISC_BASE 0x600
		#elif defined(CONFIG_ARCH_MDM9640)
		#define PCIE_VENDOR_ID_RCP 0x17cb
		#define PCIE_DEVICE_ID_RCP 0x0301

		#define PCIE20_PARF_DBI_BASE_ADDR 0x168
		#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C

		#define PCIE_N_PCS_STATUS(n, m) (PCS_PORT(n, m) + 0x128)

		#define TX_BASE 0x200
		#define RX_BASE 0x400
		#define PCS_BASE 0x600
		#define PCS_MISC_BASE 0
		#else
		#define PCIE_VENDOR_ID_RCP 0x17cb
		#define PCIE_DEVICE_ID_RCP 0x0104
		@@ -64,6 +79,8 @@
		#define PCIE20_PARF_DBI_BASE_ADDR 0x168
		#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C

		#define PCIE_N_PCS_STATUS(n, m) (PCS_PORT(n, m) + 0x174)

		#define TX_BASE 0x1000
		#define RX_BASE 0x1200
		#define PCS_BASE 0x1400
		@@ -169,7 +186,6 @@
		#define PCIE_N_TEST_CONTROL5(n, m) (PCS_PORT(n, m) + 0x120)
		#define PCIE_N_TEST_CONTROL6(n, m) (PCS_PORT(n, m) + 0x124)
		#define PCIE_N_TEST_CONTROL7(n, m) (PCS_PORT(n, m) + 0x128)
		#define PCIE_N_PCS_STATUS(n, m) (PCS_PORT(n, m) + 0x174)
		#define PCIE_N_DEBUG_BUS_0_STATUS(n, m) (PCS_PORT(n, m) + 0x198)
		#define PCIE_N_DEBUG_BUS_1_STATUS(n, m) (PCS_PORT(n, m) + 0x19C)
		#define PCIE_N_DEBUG_BUS_2_STATUS(n, m) (PCS_PORT(n, m) + 0x1A0)
		@@ -1508,6 +1524,9 @@ static void pcie_pcs_port_phy_init(struct msm_pcie_dev_t *dev)
		struct msm_pcie_phy_info_t *phy_seq;
		u8 common_phy;

		if (dev->phy_ver == 0x90)
		return;

		PCIE_DBG(dev, "RC%d: Initializing PCIe PHY Port\n", dev->rc_idx);

		if (dev->common_phy)
		@@ -1618,6 +1637,15 @@ static void pcie_pcs_port_phy_init(struct msm_pcie_dev_t *dev)

		static bool pcie_phy_is_ready(struct msm_pcie_dev_t *dev)
		{
		if (dev->phy_ver == 0x90) {
		if (readl_relaxed(dev->phy +
		PCIE_N_PCS_STATUS(dev->rc_idx, dev->common_phy)) &
		BIT(6))
		return false;
		else
		return true;
		}

		if (!(readl_relaxed(dev->phy + PCIE_COM_PCS_READY_STATUS) & 0x1))
		return false;
		else