Loading arch/arm/boot/dts/qcom/sdx20-usb.dtsi +1 −2 Original line number Diff line number Diff line Loading @@ -142,12 +142,11 @@ phy_type = "utmi"; qcom,secure-level-shifter-update; clocks = <&clock_gcc clk_ln_bb_clk>, <&clock_gcc clk_gcc_qusb_ref_clk>, <&clock_gcc clk_gcc_usb_phy_cfg_ahb_clk>, <&clock_gcc clk_gcc_qusb2a_phy_reset>, <&clock_gcc clk_gcc_sys_noc_usb3_axi_clk>; clock-names = "ref_clk_src", "ref_clk", "cfg_ahb_clk", clock-names = "ref_clk_src", "cfg_ahb_clk", "phy_reset", "iface_clk"; }; Loading Loading
arch/arm/boot/dts/qcom/sdx20-usb.dtsi +1 −2 Original line number Diff line number Diff line Loading @@ -142,12 +142,11 @@ phy_type = "utmi"; qcom,secure-level-shifter-update; clocks = <&clock_gcc clk_ln_bb_clk>, <&clock_gcc clk_gcc_qusb_ref_clk>, <&clock_gcc clk_gcc_usb_phy_cfg_ahb_clk>, <&clock_gcc clk_gcc_qusb2a_phy_reset>, <&clock_gcc clk_gcc_sys_noc_usb3_axi_clk>; clock-names = "ref_clk_src", "ref_clk", "cfg_ahb_clk", clock-names = "ref_clk_src", "cfg_ahb_clk", "phy_reset", "iface_clk"; }; Loading