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Commit bad009fe authored by Huacai Chen's avatar Huacai Chen Committed by Linus Torvalds
Browse files

MIPS: fix case mismatch in local_r4k_flush_icache_range() 



Currently, Loongson-2 call protected_blast_icache_range() and others
call protected_loongson23_blast_icache_range(), but I think the correct
behavior should be the opposite.  BTW, Loongson-3's cache-ops is
compatible with MIPS64, but not compatible with Loongson-2.  So, rename
xxx_loongson23_yyy things to xxx_loongson2_yyy.

The patch fixes early boot hang with 3.13-rc1, introduced in commit
14bd8c08 ("MIPS: Loongson: Get rid of Loongson 2 #ifdefery all over
arch/mips").

Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
Signed-off-by: default avatarAaro Koskinen <aaro.koskinen@iki.fi>
Reviewed-by: default avatarAurelien Jarno <aurelien@aurel32.net>
Acked-by: default avatarJohn Crispin <blogic@openwrt.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent 70f2fe3a

arch/mips/include/asm/cacheops.h

+1 −1
Original line number Diff line number Diff line
@@ -83,6 +83,6 @@ 
/*

 * Loongson2-specific cacheops

 */

#define Hit_Invalidate_I_Loongson23	0x00

#define Hit_Invalidate_I_Loongson2	0x00



#endif	/* __ASM_CACHEOPS_H */

arch/mips/include/asm/r4kcache.h

+4 −4
Original line number Diff line number Diff line
@@ -165,7 +165,7 @@ static inline void flush_icache_line(unsigned long addr) 
	__iflush_prologue

	switch (boot_cpu_type()) {

	case CPU_LOONGSON2:

		cache_op(Hit_Invalidate_I_Loongson23, addr);

		cache_op(Hit_Invalidate_I_Loongson2, addr);

		break;



	default:
@@ -219,7 +219,7 @@ static inline void protected_flush_icache_line(unsigned long addr) 
{

	switch (boot_cpu_type()) {

	case CPU_LOONGSON2:

		protected_cache_op(Hit_Invalidate_I_Loongson23, addr);

		protected_cache_op(Hit_Invalidate_I_Loongson2, addr);

		break;



	default:
@@ -452,8 +452,8 @@ static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, 
__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )

__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )

__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )

__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson23, \

	protected_, loongson23_)

__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \

	protected_, loongson2_)

__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )

__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )

/* blast_inv_dcache_range */

arch/mips/mm/c-r4k.c

+2 −2
Original line number Diff line number Diff line
@@ -580,11 +580,11 @@ static inline void local_r4k_flush_icache_range(unsigned long start, unsigned lo 
	else {

		switch (boot_cpu_type()) {

		case CPU_LOONGSON2:

			protected_blast_icache_range(start, end);

			protected_loongson2_blast_icache_range(start, end);

			break;



		default:

			protected_loongson23_blast_icache_range(start, end);

			protected_blast_icache_range(start, end);

			break;

		}

	}