Loading drivers/ssb/driver_pcicore.c +43 −0 Original line number Diff line number Diff line Loading @@ -467,6 +467,49 @@ static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy) } } #if 0 //done but not used yet static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address) { const u16 mdio_control = 0x128; const u16 mdio_data = 0x12C; int max_retries = 10; u16 ret = 0; u32 v; int i; v = 0x80; /* Enable Preamble Sequence */ v |= 0x2; /* MDIO Clock Divisor */ pcicore_write32(pc, mdio_control, v); if (pc->dev->id.revision >= 10) { max_retries = 200; ssb_pcie_mdio_set_phy(pc, device); } v = (1 << 30); /* Start of Transaction */ v |= (1 << 29); /* Read Transaction */ v |= (1 << 17); /* Turnaround */ if (pc->dev->id.revision < 10) v |= (u32)device << 22; v |= (u32)address << 18; pcicore_write32(pc, mdio_data, v); /* Wait for the device to complete the transaction */ udelay(10); for (i = 0; i < 200; i++) { v = pcicore_read32(pc, mdio_control); if (v & 0x100 /* Trans complete */) { udelay(10); ret = pcicore_read32(pc, mdio_data); break; } msleep(1); } pcicore_write32(pc, mdio_control, 0); return ret; } #endif static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device, u8 address, u16 data) { Loading Loading
drivers/ssb/driver_pcicore.c +43 −0 Original line number Diff line number Diff line Loading @@ -467,6 +467,49 @@ static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy) } } #if 0 //done but not used yet static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address) { const u16 mdio_control = 0x128; const u16 mdio_data = 0x12C; int max_retries = 10; u16 ret = 0; u32 v; int i; v = 0x80; /* Enable Preamble Sequence */ v |= 0x2; /* MDIO Clock Divisor */ pcicore_write32(pc, mdio_control, v); if (pc->dev->id.revision >= 10) { max_retries = 200; ssb_pcie_mdio_set_phy(pc, device); } v = (1 << 30); /* Start of Transaction */ v |= (1 << 29); /* Read Transaction */ v |= (1 << 17); /* Turnaround */ if (pc->dev->id.revision < 10) v |= (u32)device << 22; v |= (u32)address << 18; pcicore_write32(pc, mdio_data, v); /* Wait for the device to complete the transaction */ udelay(10); for (i = 0; i < 200; i++) { v = pcicore_read32(pc, mdio_control); if (v & 0x100 /* Trans complete */) { udelay(10); ret = pcicore_read32(pc, mdio_data); break; } msleep(1); } pcicore_write32(pc, mdio_control, 0); return ret; } #endif static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device, u8 address, u16 data) { Loading