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Commit ba2d0f2b authored by Thomas Gleixner's avatar Thomas Gleixner Committed by H. Peter Anvin
Browse files

x86, mce: Cleanup symbols in intel thermal codes 



Decode magic constants and turn them into symbols.

[ Cleanup to use symbols already exists - HS ]

[ Impact: cleanup ]

Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
Signed-off-by: default avatarHidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
parent b659294b

arch/x86/include/asm/msr-index.h

+7 −0
Original line number Diff line number Diff line
@@ -208,7 +208,14 @@ 


#define MSR_IA32_THERM_CONTROL		0x0000019a

#define MSR_IA32_THERM_INTERRUPT	0x0000019b



#define THERM_INT_LOW_ENABLE		(1 << 0)

#define THERM_INT_HIGH_ENABLE		(1 << 1)



#define MSR_IA32_THERM_STATUS		0x0000019c



#define THERM_STATUS_PROCHOT		(1 << 0)



#define MSR_IA32_MISC_ENABLE		0x000001a0



/* MISC_ENABLE bits: architectural */

arch/x86/kernel/cpu/mcheck/mce_intel.c

+5 −4
Original line number Diff line number Diff line
@@ -32,13 +32,13 @@ void intel_init_thermal(struct cpuinfo_x86 *c) 
	 */

	rdmsr(MSR_IA32_MISC_ENABLE, l, h);

	h = apic_read(APIC_LVTTHMR);

	if ((l & (1 << 3)) && (h & APIC_DM_SMI)) {

	if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) {

		printk(KERN_DEBUG

		       "CPU%d: Thermal monitoring handled by SMI\n", cpu);

		return;

	}



	if (cpu_has(c, X86_FEATURE_TM2) && (l & (1 << 13)))

	if (cpu_has(c, X86_FEATURE_TM2) && (l & MSR_IA32_MISC_ENABLE_TM2))

		tm2 = 1;



	/* Check whether a vector already exists */
@@ -54,12 +54,13 @@ void intel_init_thermal(struct cpuinfo_x86 *c) 
	apic_write(APIC_LVTTHMR, h);



	rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);

	wrmsr(MSR_IA32_THERM_INTERRUPT, l | 0x03, h);

	wrmsr(MSR_IA32_THERM_INTERRUPT,

		l | (THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE), h);



	intel_set_thermal_handler();



	rdmsr(MSR_IA32_MISC_ENABLE, l, h);

	wrmsr(MSR_IA32_MISC_ENABLE, l | (1 << 3), h);

	wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h);



	/* Unmask the thermal vector: */

	l = apic_read(APIC_LVTTHMR);

arch/x86/kernel/cpu/mcheck/mce_intel_64.c

+1 −1
Original line number Diff line number Diff line
@@ -29,7 +29,7 @@ asmlinkage void smp_thermal_interrupt(void) 
	irq_enter();



	rdmsrl(MSR_IA32_THERM_STATUS, msr_val);

	if (therm_throt_process(msr_val & 1))

	if (therm_throt_process(msr_val & THERM_STATUS_PROCHOT))

		mce_log_therm_throt_event(msr_val);



	inc_irq_stat(irq_thermal_count);

arch/x86/kernel/cpu/mcheck/p4.c

+1 −1
Original line number Diff line number Diff line
@@ -51,7 +51,7 @@ static void intel_thermal_interrupt(struct pt_regs *regs) 
	ack_APIC_irq();



	rdmsrl(MSR_IA32_THERM_STATUS, msr_val);

	therm_throt_process(msr_val & 0x1);

	therm_throt_process(msr_val & THERM_STATUS_PROCHOT);

}



/* Thermal interrupt handler for this CPU setup: */