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Commit ba00e2e5 authored by Jonas Gorski's avatar Jonas Gorski Committed by John Crispin
Browse files

MIPS: BCM63XX: use the new reset helper 



Use the new reset helper where appropriate.

Signed-off-by: default avatarJonas Gorski <jonas.gorski@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4453


Signed-off-by: default avatarJohn Crispin <blogic@openwrt.org>
parent 799faa62

arch/mips/bcm63xx/clk.c

+5 −14
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ 
#include <bcm63xx_cpu.h>

#include <bcm63xx_io.h>

#include <bcm63xx_regs.h>

#include <bcm63xx_reset.h>

#include <bcm63xx_clk.h>



static DEFINE_MUTEX(clocks_mutex);
@@ -124,15 +125,10 @@ static void enetsw_set(struct clk *clk, int enable) 
			CKCTL_6368_SWPKT_USB_EN |

			CKCTL_6368_SWPKT_SAR_EN, enable);

	if (enable) {

		u32 val;



		/* reset switch core afer clock change */

		val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);

		val &= ~SOFTRESET_6368_ENETSW_MASK;

		bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);

		bcm63xx_core_set_reset(BCM63XX_RESET_ENETSW, 1);

		msleep(10);

		val |= SOFTRESET_6368_ENETSW_MASK;

		bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);

		bcm63xx_core_set_reset(BCM63XX_RESET_ENETSW, 0);

		msleep(10);

	}

}
@@ -222,15 +218,10 @@ static void xtm_set(struct clk *clk, int enable) 
			CKCTL_6368_SWPKT_SAR_EN, enable);



	if (enable) {

		u32 val;



		/* reset sar core afer clock change */

		val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);

		val &= ~SOFTRESET_6368_SAR_MASK;

		bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);

		bcm63xx_core_set_reset(BCM63XX_RESET_SAR, 1);

		mdelay(1);

		val |= SOFTRESET_6368_SAR_MASK;

		bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);

		bcm63xx_core_set_reset(BCM63XX_RESET_SAR, 0);

		mdelay(1);

	}

}

arch/mips/pci/pci-bcm63xx.c

+6 −13
Original line number Diff line number Diff line
@@ -14,6 +14,8 @@ 
#include <linux/clk.h>

#include <asm/bootinfo.h>



#include <bcm63xx_reset.h>



#include "pci-bcm63xx.h"



/*
@@ -126,23 +128,14 @@ static void __init bcm63xx_reset_pcie(void) 
	bcm_misc_writel(val, MISC_SERDES_CTRL_REG);



	/* reset the PCIe core */

	val = bcm_perf_readl(PERF_SOFTRESET_6328_REG);



	val &= ~SOFTRESET_6328_PCIE_MASK;

	val &= ~SOFTRESET_6328_PCIE_CORE_MASK;

	val &= ~SOFTRESET_6328_PCIE_HARD_MASK;

	val &= ~SOFTRESET_6328_PCIE_EXT_MASK;

	bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);

	bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1);

	bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 1);

	mdelay(10);



	val |= SOFTRESET_6328_PCIE_MASK;

	val |= SOFTRESET_6328_PCIE_CORE_MASK;

	val |= SOFTRESET_6328_PCIE_HARD_MASK;

	bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);

	bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 0);

	mdelay(10);



	val |= SOFTRESET_6328_PCIE_EXT_MASK;

	bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);

	bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 0);

	mdelay(200);

}