Loading arch/arm/boot/dts/qcom/mdmfermium-cdp.dtsi +4 −0 Original line number Diff line number Diff line Loading @@ -30,3 +30,7 @@ &spi_1 { status = "ok"; }; &blsp1_uart3 { status = "ok"; }; arch/arm/boot/dts/qcom/mdmfermium-mtp.dtsi +4 −0 Original line number Diff line number Diff line Loading @@ -30,3 +30,7 @@ &spi_1 { status = "ok"; }; &blsp1_uart3 { status = "ok"; }; arch/arm/boot/dts/qcom/mdmfermium-pinctrl.dtsi +27 −0 Original line number Diff line number Diff line Loading @@ -33,6 +33,33 @@ }; }; blsp1_uart3_active: blsp1_uart3_active { mux { pins = "gpio0", "gpio1", "gpio2", "gpio3"; function = "blsp_uart3"; }; config { pins = "gpio0", "gpio1", "gpio2", "gpio3"; drive-strength = <2>; bias-disable; }; }; blsp1_uart3_sleep: blsp1_uart3_sleep { mux { pins = "gpio0", "gpio1", "gpio2", "gpio3"; function = "gpio"; }; config { pins = "gpio0", "gpio1", "gpio2", "gpio3"; drive-strength = <2>; bias-disable; }; }; spi1 { spi1_default: spi1_default { Loading arch/arm/boot/dts/qcom/mdmfermium.dtsi +36 −0 Original line number Diff line number Diff line Loading @@ -335,6 +335,42 @@ status = "disabled"; }; blsp1_uart3: uart@78b1000 { compatible = "qcom,msm-hsuart-v14"; reg = <0x78b1000 0x200>, <0x7884000 0x2b000>; reg-names = "core_mem", "bam_mem"; interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; #address-cells = <0>; interrupt-parent = <&blsp1_uart3>; interrupts = <0 1 2>; #interrupt-cells = <1>; interrupt-map-mask = <0xffffffff>; interrupt-map = <0 &intc 0 119 0 1 &intc 0 238 0 2 &tlmm_pinmux 1 0>; qcom,inject-rx-on-wakeup; qcom,rx-char-to-inject = <0xFD>; qcom,bam-tx-ep-pipe-index = <4>; qcom,bam-rx-ep-pipe-index = <5>; qcom,master-id = <86>; clock-names = "core_clk", "iface_clk"; clocks = <&clock_gcc clk_gcc_blsp1_uart3_apps_clk>, <&clock_gcc clk_gcc_blsp1_ahb_clk>; pinctrl-names = "sleep", "default"; pinctrl-0 = <&blsp1_uart3_sleep>; pinctrl-1 = <&blsp1_uart3_active>; qcom,msm-bus,name = "blsp1_uart3"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <86 512 0 0>, <86 512 500 800>; status = "disabled"; }; usb_otg: usb@78d9000 { compatible = "qcom,hsusb-otg"; reg = <0x78d9000 0x400>, <0x6c000 0x200>; Loading Loading
arch/arm/boot/dts/qcom/mdmfermium-cdp.dtsi +4 −0 Original line number Diff line number Diff line Loading @@ -30,3 +30,7 @@ &spi_1 { status = "ok"; }; &blsp1_uart3 { status = "ok"; };
arch/arm/boot/dts/qcom/mdmfermium-mtp.dtsi +4 −0 Original line number Diff line number Diff line Loading @@ -30,3 +30,7 @@ &spi_1 { status = "ok"; }; &blsp1_uart3 { status = "ok"; };
arch/arm/boot/dts/qcom/mdmfermium-pinctrl.dtsi +27 −0 Original line number Diff line number Diff line Loading @@ -33,6 +33,33 @@ }; }; blsp1_uart3_active: blsp1_uart3_active { mux { pins = "gpio0", "gpio1", "gpio2", "gpio3"; function = "blsp_uart3"; }; config { pins = "gpio0", "gpio1", "gpio2", "gpio3"; drive-strength = <2>; bias-disable; }; }; blsp1_uart3_sleep: blsp1_uart3_sleep { mux { pins = "gpio0", "gpio1", "gpio2", "gpio3"; function = "gpio"; }; config { pins = "gpio0", "gpio1", "gpio2", "gpio3"; drive-strength = <2>; bias-disable; }; }; spi1 { spi1_default: spi1_default { Loading
arch/arm/boot/dts/qcom/mdmfermium.dtsi +36 −0 Original line number Diff line number Diff line Loading @@ -335,6 +335,42 @@ status = "disabled"; }; blsp1_uart3: uart@78b1000 { compatible = "qcom,msm-hsuart-v14"; reg = <0x78b1000 0x200>, <0x7884000 0x2b000>; reg-names = "core_mem", "bam_mem"; interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; #address-cells = <0>; interrupt-parent = <&blsp1_uart3>; interrupts = <0 1 2>; #interrupt-cells = <1>; interrupt-map-mask = <0xffffffff>; interrupt-map = <0 &intc 0 119 0 1 &intc 0 238 0 2 &tlmm_pinmux 1 0>; qcom,inject-rx-on-wakeup; qcom,rx-char-to-inject = <0xFD>; qcom,bam-tx-ep-pipe-index = <4>; qcom,bam-rx-ep-pipe-index = <5>; qcom,master-id = <86>; clock-names = "core_clk", "iface_clk"; clocks = <&clock_gcc clk_gcc_blsp1_uart3_apps_clk>, <&clock_gcc clk_gcc_blsp1_ahb_clk>; pinctrl-names = "sleep", "default"; pinctrl-0 = <&blsp1_uart3_sleep>; pinctrl-1 = <&blsp1_uart3_active>; qcom,msm-bus,name = "blsp1_uart3"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <86 512 0 0>, <86 512 500 800>; status = "disabled"; }; usb_otg: usb@78d9000 { compatible = "qcom,hsusb-otg"; reg = <0x78d9000 0x400>, <0x6c000 0x200>; Loading