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Commit b93ccbf2 authored by Vikram Mulukutla's avatar Vikram Mulukutla Committed by Devesh Jhunjhunwala
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clk: msm: clock-cpu-8996: Increase CBF PLL post-divider to 4 for 8996pro 



To open up the frequency range from 150 to 300MHz, change
the fixed CBF PLL post divider from 2 to 4. That way, to
generate frequencies less than 300MHz, the VCO can be run
at 4x with the CBF mux set to use the main output.

While we're here, add the cbf_pll_main clock to the lookup
table.

CRs-Fixed: 980903
Change-Id: I9f70f18e01199c41e1940857afb7bdd477c1c04c
Signed-off-by: default avatarVikram Mulukutla <markivx@codeaurora.org>
parent 753b4916

drivers/clk/msm/clock-cpu-8996.c

+20 −3
Original line number Diff line number Diff line
@@ -535,6 +535,7 @@ struct cpu_clk_8996 { 
	struct pm_qos_request req;

	bool do_half_rate;

	bool has_acd;

	int postdiv;

};



static inline struct cpu_clk_8996 *to_cpu_clk_8996(struct clk *c)
@@ -705,12 +706,12 @@ static int cpu_clk_8996_set_rate(struct clk *c, unsigned long rate) 
		&& c->rate > 600000000 && rate < 600000000) {

		if (!cpu_clocks_v3)

			mutex_lock(&scm_lmh_lock);

		ret = clk_set_rate(c->parent, c->rate/2);

		ret = clk_set_rate(c->parent, c->rate/cpuclk->postdiv);

		if (!cpu_clocks_v3)

			mutex_unlock(&scm_lmh_lock);

		if (ret) {

			pr_err("failed to set rate %lu on %s (%d)\n",

				c->rate/2, c->dbg_name, ret);

				c->rate/cpuclk->postdiv, c->dbg_name, ret);

			goto fail;

		}

	}
@@ -781,6 +782,7 @@ static struct cpu_clk_8996 pwrcl_clk = { 
	.cpu_reg_mask = 0x3,

	.pm_qos_latency = PWRCL_LATENCY_NO_L2_PC_US,

	.do_half_rate = true,

	.postdiv = 2,

	.c = {

		.parent = &pwrcl_hf_mux.c,

		.dbg_name = "pwrcl_clk",
@@ -800,6 +802,7 @@ static struct cpu_clk_8996 perfcl_clk = { 
	.n_alt_pll_freqs = ARRAY_SIZE(alt_pll_perfcl_freqs),

	.pm_qos_latency = PERFCL_LATENCY_NO_L2_PC_US,

	.do_half_rate = true,

	.postdiv = 2,

	.c = {

		.parent = &perfcl_hf_mux.c,

		.dbg_name = "perfcl_clk",
@@ -984,6 +987,7 @@ static struct mux_clk cbf_hf_mux = { 


static struct cpu_clk_8996 cbf_clk = {

	.do_half_rate = true,

	.postdiv = 2,

	.c = {

		.parent = &cbf_hf_mux.c,

		.dbg_name = "cbf_clk",
@@ -1038,6 +1042,7 @@ static struct clk_lookup cpu_clocks_8996[] = { 
	CLK_LIST(perfcl_lf_mux),



	CLK_LIST(cbf_pll),

	CLK_LIST(cbf_pll_main),

	CLK_LIST(cbf_hf_mux),

	CLK_LIST(cbf_clk),
@@ -1273,6 +1278,15 @@ static void populate_opp_table(struct platform_device *pdev) 
	    "Failed to add OPP levels for CBF\n");

}



static void cpu_clock_8996_pro_fixup(void)

{

	cbf_pll.vals.post_div_masked = 0x300;

	cbf_pll_main.data.max_div = 4;

	cbf_pll_main.data.min_div = 4;

	cbf_pll_main.data.div = 4;

	cbf_clk.postdiv = 4;

}



static int perfclspeedbin;



unsigned long pwrcl_early_boot_rate = 883200000;
@@ -1535,6 +1549,9 @@ int __init cpu_clock_8996_early_init(void) 
		cbf_pll.vals.test_ctl_lo_val = 0x1C000000;

	}



	if (cpu_clocks_pro)

		cpu_clock_8996_pro_fixup();



	/*

	 * We definitely don't want to parse DT here - this is too early and in

	 * the critical path for boot timing. Just ioremap the bases.

include/dt-bindings/clock/msm-clocks-8996.h

+1 −0
Original line number Diff line number Diff line
@@ -531,6 +531,7 @@ 
#define clk_perfcl_hf_mux 0x9e8bbe59

#define clk_perfcl_lf_mux 0x2f9c278d

#define clk_cbf_pll 0xfe2e96a3

#define clk_cbf_pll_main 0x2b05cf95

#define clk_cbf_hf_mux 0x71244f73

#define clk_cbf_clk 0x48e9e16b

#define clk_xo_ao 0x428c856d