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Commit b8660cee authored by Hemant Kumar's avatar Hemant Kumar
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ARM: dts: msm: Add cfg_ahb_clk reference with USB3 for msmcobalt 



cfg_ahb_clk reference is required with USB controller driver to access
AHB2PHY register. Hence add cfg_ahb_clk reference with USB3 device node.

Change-Id: I294214dde4b4392f998b0e2ffefa5163cbcb07c7
Signed-off-by: default avatarHemant Kumar <hemantk@codeaurora.org>
parent 049b7256

arch/arm/boot/dts/qcom/msmcobalt.dtsi

+2 −1
Original line number Original line Diff line number Diff line
@@ -711,10 +711,11 @@ 
			<&clock_gcc clk_gcc_aggre1_usb3_axi_clk>,

			<&clock_gcc clk_gcc_aggre1_usb3_axi_clk>,

			<&clock_gcc clk_gcc_usb30_mock_utmi_clk>,

			<&clock_gcc clk_gcc_usb30_mock_utmi_clk>,

			<&clock_gcc clk_gcc_usb30_sleep_clk>,

			<&clock_gcc clk_gcc_usb30_sleep_clk>,

			<&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>,

			<&clock_gcc clk_cxo_dwc3_clk>;

			<&clock_gcc clk_cxo_dwc3_clk>;





		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",

		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",

				"utmi_clk", "sleep_clk", "xo";

				"utmi_clk", "sleep_clk", "cfg_ahb_clk", "xo";





		dwc3@a800000 {

		dwc3@a800000 {

			compatible = "snps,dwc3";

			compatible = "snps,dwc3";