Loading arch/arm/boot/dts/qcom/msm8937-pinctrl.dtsi +30 −0 Original line number Diff line number Diff line Loading @@ -80,6 +80,36 @@ }; }; i2c_3 { i2c_3_active: i2c_3_active { /* active state */ mux { pins = "gpio10", "gpio11"; function = "blsp_i2c3"; }; config { pins = "gpio10", "gpio11"; drive-strength = <2>; bias-disable; }; }; i2c_3_sleep: i2c_3_sleep { /* suspended state */ mux { pins = "gpio10", "gpio11"; function = "gpio"; }; config { pins = "gpio10", "gpio11"; drive-strength = <2>; bias-pull-down; }; }; }; i2c_5 { i2c_5_active: i2c_5_active { /* active state */ Loading arch/arm/boot/dts/qcom/msm8937.dtsi +27 −0 Original line number Diff line number Diff line Loading @@ -96,6 +96,7 @@ spi3 = &spi_3; sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ sdhc2 = &sdhc_2; /* SDC2 for SD card */ i2c3 = &i2c_3; }; soc: soc { }; Loading Loading @@ -480,6 +481,32 @@ }; }; i2c_3: i2c@78b7000 { /* BLSP1 QUP3 */ compatible = "qcom,i2c-msm-v2"; #address-cells = <1>; #size-cells = <0>; reg-names = "qup_phys_addr"; reg = <0x78b7000 0x600>; interrupt-names = "qup_irq"; interrupts = <0 97 0>; qcom,clk-freq-out = <400000>; qcom,clk-freq-in = <19200000>; clock-names = "iface_clk", "core_clk"; clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, <&clock_gcc clk_gcc_blsp1_qup3_i2c_apps_clk>; pinctrl-names = "i2c_active", "i2c_sleep"; pinctrl-0 = <&i2c_3_active>; pinctrl-1 = <&i2c_3_sleep>; qcom,noise-rjct-scl = <0>; qcom,noise-rjct-sda = <0>; qcom,master-id = <86>; dmas = <&dma_blsp1 8 64 0x20000020 0x20>, <&dma_blsp1 9 32 0x20000020 0x20>; dma-names = "tx", "rx"; status = "disabled"; }; i2c_5: i2c@7af5000 { /* BLSP2 QUP1 */ compatible = "qcom,i2c-msm-v2"; #address-cells = <1>; Loading Loading
arch/arm/boot/dts/qcom/msm8937-pinctrl.dtsi +30 −0 Original line number Diff line number Diff line Loading @@ -80,6 +80,36 @@ }; }; i2c_3 { i2c_3_active: i2c_3_active { /* active state */ mux { pins = "gpio10", "gpio11"; function = "blsp_i2c3"; }; config { pins = "gpio10", "gpio11"; drive-strength = <2>; bias-disable; }; }; i2c_3_sleep: i2c_3_sleep { /* suspended state */ mux { pins = "gpio10", "gpio11"; function = "gpio"; }; config { pins = "gpio10", "gpio11"; drive-strength = <2>; bias-pull-down; }; }; }; i2c_5 { i2c_5_active: i2c_5_active { /* active state */ Loading
arch/arm/boot/dts/qcom/msm8937.dtsi +27 −0 Original line number Diff line number Diff line Loading @@ -96,6 +96,7 @@ spi3 = &spi_3; sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ sdhc2 = &sdhc_2; /* SDC2 for SD card */ i2c3 = &i2c_3; }; soc: soc { }; Loading Loading @@ -480,6 +481,32 @@ }; }; i2c_3: i2c@78b7000 { /* BLSP1 QUP3 */ compatible = "qcom,i2c-msm-v2"; #address-cells = <1>; #size-cells = <0>; reg-names = "qup_phys_addr"; reg = <0x78b7000 0x600>; interrupt-names = "qup_irq"; interrupts = <0 97 0>; qcom,clk-freq-out = <400000>; qcom,clk-freq-in = <19200000>; clock-names = "iface_clk", "core_clk"; clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, <&clock_gcc clk_gcc_blsp1_qup3_i2c_apps_clk>; pinctrl-names = "i2c_active", "i2c_sleep"; pinctrl-0 = <&i2c_3_active>; pinctrl-1 = <&i2c_3_sleep>; qcom,noise-rjct-scl = <0>; qcom,noise-rjct-sda = <0>; qcom,master-id = <86>; dmas = <&dma_blsp1 8 64 0x20000020 0x20>, <&dma_blsp1 9 32 0x20000020 0x20>; dma-names = "tx", "rx"; status = "disabled"; }; i2c_5: i2c@7af5000 { /* BLSP2 QUP1 */ compatible = "qcom,i2c-msm-v2"; #address-cells = <1>; Loading