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Commit b8367b88 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: add the CoreSight componenets for msmgold"

parents 200cafd6 4ad309b7

arch/arm/boot/dts/qcom/msmgold-coresight.dtsi

0 → 100644
+786 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2015, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



&soc {

	tmc_etr: tmc@6028000 {

		compatible = "arm,coresight-tmc";

		reg = <0x6028000 0x1000>,

		      <0x6044000 0x15000>;

		reg-names = "tmc-base", "bam-base";

		interrupts = <0 166 0>;

		interrupt-names = "byte-cntr-irq";



		qcom,memory-size = <0x100000>;

		qcom,sg-enable;

		qcom,force-reg-dump;



		coresight-id = <0>;

		coresight-name = "coresight-tmc-etr";

		coresight-nr-inports = <1>;

		coresight-ctis = <&cti0 &cti8>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	replicator: replicator@6026000 {

		compatible = "qcom,coresight-replicator";

		reg = <0x6026000 0x1000>;

		reg-names = "replicator-base";



		coresight-id = <2>;

		coresight-name = "coresight-replicator";

		coresight-nr-inports = <1>;

		coresight-outports = <0>;

		coresight-child-list = <&tmc_etr>;

		coresight-child-ports = <0 0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	tmc_etf: tmc@6027000 {

		compatible = "arm,coresight-tmc";

		reg = <0x6027000 0x1000>;

		reg-names = "tmc-base";



		coresight-id = <3>;

		coresight-name = "coresight-tmc-etf";

		coresight-nr-inports = <1>;

		coresight-outports = <0>;

		coresight-child-list = <&replicator>;

		coresight-child-ports = <0>;

		coresight-default-sink;

		coresight-ctis = <&cti0 &cti8>;

		qcom,force-reg-dump;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	funnel_in0: funnel@6021000 {

		compatible = "arm,coresight-funnel";

		reg = <0x6021000 0x1000>;

		reg-names = "funnel-base";



		coresight-id = <4>;

		coresight-name = "coresight-funnel-in0";

		coresight-nr-inports = <8>;

		coresight-outports = <0>;

		coresight-child-list = <&tmc_etf>;

		coresight-child-ports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	funnel_mm: funnel@6130000 {

		compatible = "arm,coresight-funnel";

		reg = <0x6130000 0x1000>;

		reg-names = "funnel-base";



		coresight-id = <5>;

		coresight-name = "coresight-funnel-mm";

		coresight-nr-inports = <8>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in0>;

		coresight-child-ports = <5>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	funnel_center: funnel@6100000 {

		compatible = "arm,coresight-funnel";

		reg = <0x6100000 0x1000>;

		reg-names = "funnel-base";



		coresight-id = <6>;

		coresight-name = "coresight-funnel-center";

		coresight-nr-inports = <8>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in0>;

		coresight-child-ports = <3>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	funnel_right: funnel@6120000 {

		compatible = "arm,coresight-funnel";

		reg = <0x6120000 0x1000>;

		reg-names = "funnel-base";



		coresight-id = <7>;

		coresight-name = "coresight-funnel-right";

		coresight-nr-inports = <8>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in0>;

		coresight-child-ports = <4>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	funnel_cam: funnel@6132000 {

		compatible = "arm,coresight-funnel";

		reg = <0x6132000 0x1000>;

		reg-names = "funnel-base";



		coresight-id = <8>;

		coresight-name = "coresight-funnel-cam";

		coresight-nr-inports = <8>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_mm>;

		coresight-child-ports = <4>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	funnel_apss: funnel@61a1000 {

		compatible = "arm,coresight-funnel";

		reg = <0x61a1000 0x1000>;

		reg-names = "funnel-base";



		coresight-id = <9>;

		coresight-name = "coresight-funnel-apss";

		coresight-nr-inports = <8>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_right>;

		coresight-child-ports = <2>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	etm0: etm@61bc000 {

		compatible = "arm,coresight-etmv4";

		reg = <0x61bc000 0x1000>;

		reg-names = "etm-base";



		coresight-id = <10>;

		coresight-name = "coresight-etm0";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <0>;

		coresight-etm-cpu = <&CPU0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	etm1: etm@61bd000 {

		compatible = "arm,coresight-etmv4";

		reg = <0x61bd000 0x1000>;

		reg-names = "etm-base";



		coresight-id = <11>;

		coresight-name = "coresight-etm1";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <1>;

		coresight-etm-cpu = <&CPU1>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	etm2: etm@61be000 {

		compatible = "arm,coresight-etmv4";

		reg = <0x61be000 0x1000>;

		reg-names = "etm-base";



		coresight-id = <12>;

		coresight-name = "coresight-etm2";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <2>;

		coresight-etm-cpu = <&CPU2>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	etm3: etm@61bf000 {

		compatible = "arm,coresight-etmv4";

		reg = <0x61bf000 0x1000>;

		reg-names = "etm-base";



		coresight-id = <13>;

		coresight-name = "coresight-etm3";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <3>;

		coresight-etm-cpu = <&CPU3>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	stm: stm@6002000 {

		compatible = "arm,coresight-stm";

		reg = <0x6002000 0x1000>,

		      <0x9280000 0x180000>;

		reg-names = "stm-base", "stm-data-base";



		coresight-id = <18>;

		coresight-name = "coresight-stm";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in0>;

		coresight-child-ports = <7>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti0: cti@6010000 {

		compatible = "arm,coresight-cti";

		reg = <0x6010000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <19>;

		coresight-name = "coresight-cti0";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti1: cti@6011000 {

		compatible = "arm,coresight-cti";

		reg = <0x6011000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <20>;

		coresight-name = "coresight-cti1";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti2: cti@6012000 {

		compatible = "arm,coresight-cti";

		reg = <0x6012000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <21>;

		coresight-name = "coresight-cti2";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti3: cti@6013000 {

		compatible = "arm,coresight-cti";

		reg = <0x6013000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <22>;

		coresight-name = "coresight-cti3";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti4: cti@6014000 {

		compatible = "arm,coresight-cti";

		reg = <0x6014000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <23>;

		coresight-name = "coresight-cti4";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti5: cti@6015000 {

		compatible = "arm,coresight-cti";

		reg = <0x6015000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <24>;

		coresight-name = "coresight-cti5";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti6: cti@6016000 {

		compatible = "arm,coresight-cti";

		reg = <0x6016000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <25>;

		coresight-name = "coresight-cti6";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti7: cti@6017000 {

		compatible = "arm,coresight-cti";

		reg = <0x6017000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <26>;

		coresight-name = "coresight-cti7";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti8: cti@6018000 {

		compatible = "arm,coresight-cti";

		reg = <0x6018000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <27>;

		coresight-name = "coresight-cti8";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti9: cti@6019000 {

		compatible = "arm,coresight-cti";

		reg = <0x6019000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <28>;

		coresight-name = "coresight-cti9";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti10: cti@601a000 {

		compatible = "arm,coresight-cti";

		reg = <0x601a000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <29>;

		coresight-name = "coresight-cti10";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti11: cti@601b000 {

		compatible = "arm,coresight-cti";

		reg = <0x601b000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <30>;

		coresight-name = "coresight-cti11";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti12: cti@601c000 {

		compatible = "arm,coresight-cti";

		reg = <0x601c000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <31>;

		coresight-name = "coresight-cti12";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti13: cti@601d000 {

		compatible = "arm,coresight-cti";

		reg = <0x601d000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <32>;

		coresight-name = "coresight-cti13";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti14: cti@601e000 {

		compatible = "arm,coresight-cti";

		reg = <0x601e000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <33>;

		coresight-name = "coresight-cti14";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti15: cti@601f000 {

		compatible = "arm,coresight-cti";

		reg = <0x601f000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <34>;

		coresight-name = "coresight-cti15";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti_cpu0: cti@61b8000 {

		compatible = "arm,coresight-cti";

		reg = <0x61b8000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <35>;

		coresight-name = "coresight-cti-cpu0";

		coresight-nr-inports = <0>;

		coresight-cti-cpu = <&CPU0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti_cpu1: cti@61b9000 {

		compatible = "arm,coresight-cti";

		reg = <0x61b9000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <36>;

		coresight-name = "coresight-cti-cpu1";

		coresight-nr-inports = <0>;

		coresight-cti-cpu = <&CPU1>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti_cpu2: cti@61ba000 {

		compatible = "arm,coresight-cti";

		reg = <0x61ba000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <37>;

		coresight-name = "coresight-cti-cpu2";

		coresight-nr-inports = <0>;

		coresight-cti-cpu = <&CPU2>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti_cpu3: cti@61bb000 {

		compatible = "arm,coresight-cti";

		reg = <0x61bb000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <38>;

		coresight-name = "coresight-cti-cpu3";

		coresight-nr-inports = <0>;

		coresight-cti-cpu = <&CPU3>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti_modem_cpu0: cti@6124000 {

		compatible = "arm,coresight-cti";

		reg = <0x6124000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <43>;

		coresight-name = "coresight-cti-modem-cpu0";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	/* Proto CTI */

	cti_wcn_cpu0: cti@6139000 {

		compatible = "arm,coresight-cti";

		reg = <0x6139000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <44>;

		coresight-name = "coresight-cti-wcn-cpu0";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	/* Venus CTI */

	cti_video_cpu0: cti@6134000 {

		compatible = "arm,coresight-cti";

		reg = <0x6134000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <45>;

		coresight-name = "coresight-cti-video-cpu0";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	/* LPASS CTI */

	cti_audio_cpu0: cti@613c000 {

		compatible = "arm,coresight-cti";

		reg = <0x613c000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <46>;

		coresight-name = "coresight-cti-audio-cpu0";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	/* RPM CTI */

	cti_rpm_cpu0: cti@610c000 {

		compatible = "arm,coresight-cti";

		reg = <0x610c000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <47>;

		coresight-name = "coresight-cti-rpm-cpu0";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	/* Proto ETM */

	wcn_etm0 {

		compatible = "qcom,coresight-remote-etm";



		coresight-id = <48>;

		coresight-name = "coresight-wcn-etm0";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_mm>;

		coresight-child-ports = <0>;



		qcom,inst-id = <3>;

	};



	rpm_etm0 {

		compatible = "qcom,coresight-remote-etm";



		coresight-id = <49>;

		coresight-name = "coresight-rpm-etm0";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_center>;

		coresight-child-ports = <0>;



		qcom,inst-id = <4>;

	};



	/* LPASS ETM */

	audio_etm0 {

		compatible = "qcom,coresight-remote-etm";



		coresight-id = <50>;

		coresight-name = "coresight-audio-etm0";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_mm>;

		coresight-child-ports = <5>;



		qcom,inst-id = <5>;

	};



	modem_etm0 {

		compatible = "qcom,coresight-remote-etm";



		coresight-id = <51>;

		coresight-name = "coresight-modem-etm0";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_right>;

		coresight-child-ports = <1>;



		qcom,inst-id = <2>;

	};



	csr: csr@6001000 {

		compatible = "qcom,coresight-csr";

		reg = <0x6001000 0x1000>;

		reg-names = "csr-base";



		coresight-id = <52>;

		coresight-name = "coresight-csr";

		coresight-nr-inports = <0>;

		qcom,blk-size = <1>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	dbgui: dbgui@6108000 {

		compatible = "qcom,coresight-dbgui";

		reg = <0x6108000 0x1000>;

		reg-names = "dbgui-base";



		coresight-id = <53>;

		coresight-name = "coresight-dbgui";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_center>;

		coresight-child-ports = <2>;



		qcom,dbgui-addr-offset = <0x30>;

		qcom,dbgui-data-offset = <0x130>;

		qcom,dbgui-size = <32>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	tpda: tpda@6003000 {

		compatible = "qcom,coresight-tpda";

		reg = <0x6003000 0x1000>;

		reg-names = "tpda-base";



		coresight-id = <54>;

		coresight-name = "coresight-tpda";

		coresight-nr-inports = <2>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in0>;

		coresight-child-ports = <6>;



		qcom,tpda-atid = <64>;

		qcom,cmb-elem-size = <0 32>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	tpdm_dcc: tpdm@6110000 {

		compatible = "qcom,coresight-tpdm";

		reg = <0x6110000 0x1000>;

		reg-names = "tpdm-base";



		coresight-id = <55>;

		coresight-name = "coresight-tpdm-dcc";

		coresight-nr-inports = <1>;

		coresight-outports = <0>;

		coresight-child-list = <&tpda>;

		coresight-child-ports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	hwevent: hwevent@6101000 {

		compatible = "qcom,coresight-hwevent";

		reg = <0x6101000 0x148>,

		      <0x6101fb0 0x4>,

		      <0x6121000 0x148>,

		      <0x6121fb0 0x4>,

		      <0x6131000 0x148>,

		      <0x6131fb0 0x4>,

		      <0x78c5010 0x4>,

		      <0x7885010 0x4>;

		reg-names = "center-wrapper-mux", "center-wrapper-lockaccess",

			    "right-wrapper-mux", "right-wrapper-lockaccess",

			    "mm-wrapper-mux", "mm-wrapper-lockaccess",

			    "usbbam-mux", "blsp-mux";



		coresight-id = <56>;

		coresight-name = "coresight-hwevent";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	fuse: fuse@a601c {

		compatible = "arm,coresight-fuse-v2";

		reg = <0xa601c 0x8>,

		      <0xa6004 0x4>,

		      <0xa600c 0x4>;

		reg-names = "fuse-base", "nidnt-fuse-base", "qpdi-fuse-base";



		coresight-id = <57>;

		coresight-name = "coresight-fuse";

		coresight-nr-inports = <0>;

	};

};

arch/arm/boot/dts/qcom/msmgold.dtsi

+71 −0
Original line number Diff line number Diff line
@@ -93,6 +93,7 @@ 
#include "msmgold-iommu.dtsi"

#include "msmgold-iommu-domains.dtsi"

#include "msmgold-smp2p.dtsi"

#include "msmgold-coresight.dtsi"



&soc {

	#address-cells = <1>;
@@ -513,6 +514,76 @@ 
		};

	};



	jtag_fuse: jtagfuse@a601c {

		compatible = "qcom,jtag-fuse-v2";

		reg = <0xa601c 0x8>;

		reg-names = "fuse-base";

	};



	jtag_mm0: jtagmm@61bc000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x61bc000 0x1000>,

		      <0x61b0000 0x1000>;

		reg-names = "etm-base", "debug-base";



		qcom,coresight-jtagmm-cpu = <&CPU0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	jtag_mm1: jtagmm@61bd000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x61bd000 0x1000>,

		      <0x61b2000 0x1000>;

		reg-names = "etm-base", "debug-base";



		qcom,coresight-jtagmm-cpu = <&CPU1>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	jtag_mm2: jtagmm@61be000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x61be000 0x1000>,

		      <0x61b4000 0x1000>;

		reg-names = "etm-base", "debug-base";



		qcom,coresight-jtagmm-cpu = <&CPU2>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	jtag_mm3: jtagmm@61bf000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x61bf000 0x1000>,

		      <0x61b6000 0x1000>;

		reg-names = "etm-base", "debug-base";



		qcom,coresight-jtagmm-cpu = <&CPU3>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	dcc: dcc@b3000 {

		compatible = "qcom,dcc";

		reg = <0xb3000 0x1000>,

		      <0xb4000 0x2000>;

		reg-names = "dcc-base", "dcc-ram-base";



		clocks = <&clock_gcc clk_gcc_dcc_clk>;

		clock-names = "dcc_clk";



		qcom,save-reg;

	};



	qcom,ipc-spinlock@1905000 {

		compatible = "qcom,ipc-spinlock-sfpb";

		reg = <0x1905000 0x8000>;