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Commit b8041b80 authored by Suman Tatiraju's avatar Suman Tatiraju
Browse files

msm: kgsl: Read speed bin information from device tree 



Speed bin information is sometimes written to efuses to
specify a GPU frequency plan available on a platform. The
current code only supports reading the efuses for msm8996v3.
Hence specify it in the platform device tree node to
support multiple platforms.

CRs-Fixed: 967494
Change-Id: I5db4d5a35e2700250517ea6cac3d4d736936ce9f
Signed-off-by: default avatarSuman Tatiraju <sumant@codeaurora.org>
parent d5fd12a0

Documentation/devicetree/bindings/gpu/adreno.txt

+6 −0
Original line number Diff line number Diff line
@@ -109,6 +109,12 @@ Optional Properties: 
- qcom,gpu-quirk-two-pass-use-wfi:

				Signal the GPU to set Set TWOPASSUSEWFI bit in

				A5XX_PC_DBG_ECO_CNTL (5XX only)

- qcom,gpu-speed-bin:      GPU speed bin information in the format

			   <offset mask shift>

				offset - offset of the efuse register from the base.

				mask   - mask for the relevant bits in the efuse register.

				shift  - number of bits to right shift to get the speed bin

				value.



The following properties are optional as collecting data via coresight might

not be supported for every chipset. The documentation for coresight

arch/arm/boot/dts/qcom/msm8996-v3.dtsi

+2 −1
Original line number Diff line number Diff line 
/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.

/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -100,6 +100,7 @@ 


	qcom,initial-pwrlevel = <5>;

	qcom,bus-width = <32>;

	qcom,gpu-speed-bin = <0x4130 0xe0000000 29>;



	/* Quirks */

	qcom,gpu-quirk-two-pass-use-wfi;

arch/arm/boot/dts/qcom/msm8996pro.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -861,6 +861,8 @@ 


	qcom,initial-pwrlevel = <6>;



	qcom,gpu-speed-bin = <0x413c 0x30000000 28>;



	qcom,gpu-pwrlevel-bins {

		#address-cells = <1>;

		#size-cells = <0>;

drivers/gpu/msm/adreno_a5xx.c

+9 −6
Original line number Diff line number Diff line
@@ -78,7 +78,6 @@ static int a5xx_gpmu_init(struct adreno_device *adreno_dev); 


#define A530_QFPROM_RAW_PTE_ROW0_MSB 0x134

#define A530_QFPROM_RAW_PTE_ROW2_MSB 0x144

#define A530_QFPROM_CORR_PTE_ROW0_LSB 0x4130



static void a530_efuse_leakage(struct adreno_device *adreno_dev)

{
@@ -108,12 +107,16 @@ static void a530_efuse_leakage(struct adreno_device *adreno_dev) 
static void a530_efuse_speed_bin(struct adreno_device *adreno_dev)

{

	unsigned int val;

	unsigned int speed_bin[3];

	struct kgsl_device *device = &adreno_dev->dev;



	adreno_efuse_read_u32(adreno_dev,

		A530_QFPROM_CORR_PTE_ROW0_LSB, &val);

	if (of_property_read_u32_array(device->pdev->dev.of_node,

		"qcom,gpu-speed-bin", speed_bin, 3))

		return;



	adreno_efuse_read_u32(adreno_dev, speed_bin[0], &val);



	adreno_dev->speed_bin =

		(val & 0xE0000000) >> 29;

	adreno_dev->speed_bin = (val & speed_bin[1]) >> speed_bin[2];

}



static const struct {
@@ -121,7 +124,7 @@ static const struct { 
	void (*func)(struct adreno_device *adreno_dev);

} a5xx_efuse_funcs[] = {

	{ adreno_is_a530, a530_efuse_leakage },

	{ adreno_is_a530v3, a530_efuse_speed_bin },

	{ adreno_is_a530, a530_efuse_speed_bin },

};



static void a5xx_check_features(struct adreno_device *adreno_dev)