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Commit b70c4207 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes

parents 597b97ca 52f3a41e

arch/arm/configs/omap1_defconfig

+0 −1
Original line number Diff line number Diff line
@@ -48,7 +48,6 @@ CONFIG_MACH_SX1=y 
CONFIG_MACH_NOKIA770=y

CONFIG_MACH_AMS_DELTA=y

CONFIG_MACH_OMAP_GENERIC=y

CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER=y

CONFIG_OMAP_ARM_216MHZ=y

CONFIG_OMAP_ARM_195MHZ=y

CONFIG_OMAP_ARM_192MHZ=y

arch/arm/mach-omap1/Kconfig

+0 −8
Original line number Diff line number Diff line
@@ -171,14 +171,6 @@ config MACH_OMAP_GENERIC 
comment "OMAP CPU Speed"

	depends on ARCH_OMAP1



config OMAP_CLOCKS_SET_BY_BOOTLOADER

	bool "OMAP clocks set by bootloader"

	depends on ARCH_OMAP1

	help

	  Enable this option to prevent the kernel from overriding the clock

	  frequencies programmed by bootloader for MPU, DSP, MMUs, TC,

	  internal LCD controller and MPU peripherals.



config OMAP_ARM_216MHZ

	bool "OMAP ARM 216 MHz CPU (1710 only)"

        depends on ARCH_OMAP1 && ARCH_OMAP16XX

arch/arm/mach-omap1/board-ams-delta.c

+7 −3
Original line number Diff line number Diff line
@@ -302,8 +302,6 @@ static void __init ams_delta_init(void) 
	omap_cfg_reg(J19_1610_CAM_D6);

	omap_cfg_reg(J18_1610_CAM_D7);



	iotable_init(ams_delta_io_desc, ARRAY_SIZE(ams_delta_io_desc));



	omap_board_config = ams_delta_config;

	omap_board_config_size = ARRAY_SIZE(ams_delta_config);

	omap_serial_init();
@@ -373,10 +371,16 @@ static int __init ams_delta_modem_init(void) 
}

arch_initcall(ams_delta_modem_init);



static void __init ams_delta_map_io(void)

{

	omap15xx_map_io();

	iotable_init(ams_delta_io_desc, ARRAY_SIZE(ams_delta_io_desc));

}



MACHINE_START(AMS_DELTA, "Amstrad E3 (Delta)")

	/* Maintainer: Jonathan McDowell <noodles@earth.li> */

	.atag_offset	= 0x100,

	.map_io		= omap15xx_map_io,

	.map_io		= ams_delta_map_io,

	.init_early	= omap1_init_early,

	.reserve	= omap_reserve,

	.init_irq	= omap1_init_irq,

arch/arm/mach-omap1/clock.h

+2 −1
Original line number Diff line number Diff line
@@ -17,7 +17,8 @@ 


#include <plat/clock.h>



extern int __init omap1_clk_init(void);

int omap1_clk_init(void);

void omap1_clk_late_init(void);

extern int omap1_clk_enable(struct clk *clk);

extern void omap1_clk_disable(struct clk *clk);

extern long omap1_clk_round_rate(struct clk *clk, unsigned long rate);

arch/arm/mach-omap1/clock_data.c

+34 −19
Original line number Diff line number Diff line
@@ -767,6 +767,15 @@ static struct clk_functions omap1_clk_functions = { 
	.clk_disable_unused	= omap1_clk_disable_unused,

};



static void __init omap1_show_rates(void)

{

	pr_notice("Clocking rate (xtal/DPLL1/MPU): "

			"%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",

		ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,

		ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,

		arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);

}



int __init omap1_clk_init(void)

{

	struct omap_clk *c;
@@ -835,9 +844,12 @@ int __init omap1_clk_init(void) 
	/* We want to be in syncronous scalable mode */

	omap_writew(0x1000, ARM_SYSST);



#ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER

	/* Use values set by bootloader. Determine PLL rate and recalculate

	 * dependent clocks as if kernel had changed PLL or divisors.



	/*

	 * Initially use the values set by bootloader. Determine PLL rate and

	 * recalculate dependent clocks as if kernel had changed PLL or

	 * divisors. See also omap1_clk_late_init() that can reprogram dpll1

	 * after the SRAM is initialized.

	 */

	{

		unsigned pll_ctl_val = omap_readw(DPLL_CTL);
@@ -862,25 +874,10 @@ int __init omap1_clk_init(void) 
			}

		}

	}

#else

	/* Find the highest supported frequency and enable it */

	if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {

		printk(KERN_ERR "System frequencies not set. Check your config.\n");

		/* Guess sane values (60MHz) */

		omap_writew(0x2290, DPLL_CTL);

		omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL);

		ck_dpll1.rate = 60000000;

	}

#endif

	propagate_rate(&ck_dpll1);

	/* Cache rates for clocks connected to ck_ref (not dpll1) */

	propagate_rate(&ck_ref);

	printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "

		"%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",

	       ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,

	       ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,

	       arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);



	omap1_show_rates();

	if (machine_is_omap_perseus2() || machine_is_omap_fsample()) {

		/* Select slicer output as OMAP input clock */

		omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1,
@@ -925,3 +922,21 @@ int __init omap1_clk_init(void) 


	return 0;

}



#define OMAP1_DPLL1_SANE_VALUE	60000000



void __init omap1_clk_late_init(void)

{

	if (ck_dpll1.rate >= OMAP1_DPLL1_SANE_VALUE)

		return;



	/* Find the highest supported frequency and enable it */

	if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {

		pr_err("System frequencies not set, using default. Check your config.\n");

		omap_writew(0x2290, DPLL_CTL);

		omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL);

		ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE;

	}

	propagate_rate(&ck_dpll1);

	omap1_show_rates();

}