Merge "arm64: dts: Add support for other cores for MSMTHORIUM" (b661d1f4) · Commits · e / devices / android_kernel_xiaomi_markw

arch/arm/boot/dts/qcom/msmthorium-cpu.dtsi

+77 −0

Original line number	Diff line number	Diff line
		@@ -20,12 +20,30 @@
		core0 {
		cpu = <&CPU0>;
		};
		core1 {
		cpu = <&CPU1>;
		};
		core2 {
		cpu = <&CPU2>;
		};
		core3 {
		cpu = <&CPU3>;
		};
		};

		cluster1 {
		core0 {
		cpu = <&CPU4>;
		};
		core1 {
		cpu = <&CPU5>;
		};
		core2 {
		cpu = <&CPU6>;
		};
		core3 {
		cpu = <&CPU7>;
		};
		};
		};

		@@ -44,6 +62,36 @@
		};
		};

		CPU1: cpu@1 {
		device_type = "cpu";
		compatible = "arm,cortex-a53";
		reg = <0x1>;
		enable-method = "spin-table";
		cpu-release-addr = <0x0 0x90000000>;
		qcom,acc = <&acc1>;
		next-level-cache = <&L2_0>;
		};

		CPU2: cpu@2 {
		device_type = "cpu";
		compatible = "arm,cortex-a53";
		reg = <0x2>;
		enable-method = "spin-table";
		cpu-release-addr = <0x0 0x90000000>;
		qcom,acc = <&acc2>;
		next-level-cache = <&L2_0>;
		};

		CPU3: cpu@3 {
		device_type = "cpu";
		compatible = "arm,cortex-a53";
		reg = <0x3>;
		enable-method = "spin-table";
		cpu-release-addr = <0x0 0x90000000>;
		qcom,acc = <&acc3>;
		next-level-cache = <&L2_0>;
		};

		CPU4: cpu@100 {
		device_type = "cpu";
		compatible = "arm,cortex-a53";
		@@ -59,6 +107,35 @@
		};
		};

		CPU5: cpu@101 {
		device_type = "cpu";
		compatible = "arm,cortex-a53";
		reg = <0x101>;
		enable-method = "spin-table";
		cpu-release-addr = <0x0 0x90000000>;
		qcom,acc = <&acc5>;
		next-level-cache = <&L2_1>;
		};

		CPU6: cpu@102 {
		device_type = "cpu";
		compatible = "arm,cortex-a53";
		reg = <0x102>;
		enable-method = "spin-table";
		cpu-release-addr = <0x0 0x90000000>;
		qcom,acc = <&acc6>;
		next-level-cache = <&L2_1>;
		};

		CPU7: cpu@103 {
		device_type = "cpu";
		compatible = "arm,cortex-a53";
		reg = <0x103>;
		enable-method = "spin-table";
		cpu-release-addr = <0x0 0x90000000>;
		qcom,acc = <&acc7>;
		next-level-cache = <&L2_1>;
		};
		};
		};