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Commit b5f12439 authored by Mallikarjuna Reddy Amireddy's avatar Mallikarjuna Reddy Amireddy
Browse files

ARM: dts: msm: Add crypto device tree data for msmthorium 



Add crypto drivers device tree data to dtsi file by adding qcrypto
and qcedev device node with all the necessary parameters, to enable
crypto drivers on msmthorium.

Change-Id: Ib75644b7cc295b4046b2cfac5ebfeb69eeafeef5
Signed-off-by: default avatarMallikarjuna Reddy Amireddy <mamire@codeaurora.org>
parent 2fe24b88

arch/arm/boot/dts/qcom/msmthorium.dtsi

+55 −0
Original line number Diff line number Diff line
@@ -807,6 +807,61 @@ 
		reg = <0x08600720 0x2000>;

	};



	qcom_crypto: qcrypto@720000 {

		compatible = "qcom,qcrypto";

		reg = <0x720000 0x20000>,

		      <0x704000 0x20000>;

		reg-names = "crypto-base","crypto-bam-base";

		interrupts = <0 207 0>;

		qcom,bam-pipe-pair = <2>;

		qcom,ce-hw-instance = <0>;

		qcom,ce-device = <0>;

		qcom,ce-hw-shared;

		qcom,clk-mgmt-sus-res;

		qcom,msm-bus,name = "qcrypto-noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<55 512 0 0>,

				<55 512 393600 393600>;

		clocks = <&clock_gcc clk_crypto_clk_src>,

			 <&clock_gcc clk_gcc_crypto_clk>,

			 <&clock_gcc clk_gcc_crypto_ahb_clk>,

			 <&clock_gcc clk_gcc_crypto_axi_clk>;

		clock-names = "core_clk_src", "core_clk",

				"iface_clk", "bus_clk";

		qcom,use-sw-aes-cbc-ecb-ctr-algo;

		qcom,use-sw-aes-xts-algo;

		qcom,use-sw-aes-ccm-algo;

		qcom,use-sw-ahash-algo;

		qcom,ce-opp-freq = <100000000>;

	};



	qcom_cedev: qcedev@720000 {

		compatible = "qcom,qcedev";

		reg = <0x720000 0x20000>,

		      <0x704000 0x20000>;

		reg-names = "crypto-base","crypto-bam-base";

		interrupts = <0 207 0>;

		qcom,bam-pipe-pair = <1>;

		qcom,ce-hw-instance = <0>;

		qcom,ce-device = <0>;

		qcom,ce-hw-shared;

		qcom,msm-bus,name = "qcedev-noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

			<55 512 0 0>,

			<55 512 393600 393600>;

		clocks = <&clock_gcc clk_crypto_clk_src>,

			 <&clock_gcc clk_gcc_crypto_clk>,

			 <&clock_gcc clk_gcc_crypto_ahb_clk>,

			 <&clock_gcc clk_gcc_crypto_axi_clk>;

		clock-names = "core_clk_src", "core_clk",

				"iface_clk", "bus_clk";

		qcom,ce-opp-freq = <100000000>;

	};



	qcom,ipc_router {

		compatible = "qcom,ipc_router";

		qcom,node-id = <1>;