Loading drivers/clk/msm/clock-gcc-8952.c +31 −2 Original line number Diff line number Diff line Loading @@ -766,6 +766,27 @@ static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_8937_475MHz[] = { F_END }; static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_8940_500MHz[] = { F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0), F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0), F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0), F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0), F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0), F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0), F_SLEW( 216000000, FIXED_CLK_SRC, gpll6_aux, 5, 0, 0), F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0), F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0), F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0), F_SLEW( 300000000, 600000000, gpll3, 1, 0, 0), F_SLEW( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0), F_SLEW( 375000000, 750000000, gpll3, 1, 0, 0), F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0), F_SLEW( 450000000, 900000000, gpll3, 1, 0, 0), F_SLEW( 475000000, 950000000, gpll3, 1, 0, 0), F_SLEW( 500000000, 1000000000, gpll3, 1, 0, 0), F_END }; static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_8917[] = { F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0), F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0), Loading Loading @@ -4375,9 +4396,17 @@ static int msm_gcc_probe(struct platform_device *pdev) override_for_8937(speed_bin); if (compat_bin3) { if (speed_bin) { gfx3d_clk_src.freq_tbl = ftbl_gcc_oxili_gfx3d_clk_8940_500MHz; gfx3d_clk_src.c.fmax[VDD_DIG_SUPER_TUR] = 500000000; } else { gfx3d_clk_src.freq_tbl = ftbl_gcc_oxili_gfx3d_clk_8937_475MHz; gfx3d_clk_src.c.fmax[VDD_DIG_SUPER_TUR] = 475000000; gfx3d_clk_src.c.fmax[VDD_DIG_SUPER_TUR] = 475000000; } } } else if (compat_bin2 || compat_bin4) { gpll0_clk_src.c.parent = &gpll0_clk_src_8937.c; Loading Loading
drivers/clk/msm/clock-gcc-8952.c +31 −2 Original line number Diff line number Diff line Loading @@ -766,6 +766,27 @@ static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_8937_475MHz[] = { F_END }; static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_8940_500MHz[] = { F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0), F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0), F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0), F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0), F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0), F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0), F_SLEW( 216000000, FIXED_CLK_SRC, gpll6_aux, 5, 0, 0), F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0), F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0), F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0), F_SLEW( 300000000, 600000000, gpll3, 1, 0, 0), F_SLEW( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0), F_SLEW( 375000000, 750000000, gpll3, 1, 0, 0), F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0), F_SLEW( 450000000, 900000000, gpll3, 1, 0, 0), F_SLEW( 475000000, 950000000, gpll3, 1, 0, 0), F_SLEW( 500000000, 1000000000, gpll3, 1, 0, 0), F_END }; static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_8917[] = { F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0), F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0), Loading Loading @@ -4375,9 +4396,17 @@ static int msm_gcc_probe(struct platform_device *pdev) override_for_8937(speed_bin); if (compat_bin3) { if (speed_bin) { gfx3d_clk_src.freq_tbl = ftbl_gcc_oxili_gfx3d_clk_8940_500MHz; gfx3d_clk_src.c.fmax[VDD_DIG_SUPER_TUR] = 500000000; } else { gfx3d_clk_src.freq_tbl = ftbl_gcc_oxili_gfx3d_clk_8937_475MHz; gfx3d_clk_src.c.fmax[VDD_DIG_SUPER_TUR] = 475000000; gfx3d_clk_src.c.fmax[VDD_DIG_SUPER_TUR] = 475000000; } } } else if (compat_bin2 || compat_bin4) { gpll0_clk_src.c.parent = &gpll0_clk_src_8937.c; Loading