Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit b500f680 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/kms: add regs and irq tracking bits for hpd 



Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent eed45b30

drivers/gpu/drm/radeon/r600d.h

+53 −1
Original line number Diff line number Diff line
@@ -558,6 +558,7 @@ 
#       define DC_HOT_PLUG_DETECT2_INTERRUPT              (1 << 19)

#       define DC_I2C_SW_DONE_INTERRUPT                   (1 << 20)

#       define DC_I2C_HW_DONE_INTERRUPT                   (1 << 21)

#define DISP_INTERRUPT_STATUS_CONTINUE                    0x7ee8

#define DCE3_DISP_INTERRUPT_STATUS_CONTINUE               0x7de8

#       define DC_HPD4_INTERRUPT                          (1 << 14)

#       define DC_HPD4_RX_INTERRUPT                       (1 << 15)
@@ -590,6 +591,18 @@ 
#       define DC_HPD6_INTERRUPT                          (1 << 21)

#       define DC_HPD6_RX_INTERRUPT                       (1 << 22)



#define DACA_AUTO_DETECT_CONTROL                          0x7828

#define DACB_AUTO_DETECT_CONTROL                          0x7a28

#define DCE3_DACA_AUTO_DETECT_CONTROL                     0x7028

#define DCE3_DACB_AUTO_DETECT_CONTROL                     0x7128

#       define DACx_AUTODETECT_MODE(x)                    ((x) << 0)

#       define DACx_AUTODETECT_MODE_NONE                  0

#       define DACx_AUTODETECT_MODE_CONNECT               1

#       define DACx_AUTODETECT_MODE_DISCONNECT            2

#       define DACx_AUTODETECT_FRAME_TIME_COUNTER(x)      ((x) << 8)

/* bit 18 = R/C, 17 = G/Y, 16 = B/Comp */

#       define DACx_AUTODETECT_CHECK_MASK(x)              ((x) << 16)



#define DCE3_DACA_AUTODETECT_INT_CONTROL                  0x7038

#define DCE3_DACB_AUTODETECT_INT_CONTROL                  0x7138

#define DACA_AUTODETECT_INT_CONTROL                       0x7838
@@ -597,23 +610,62 @@ 
#       define DACx_AUTODETECT_ACK                        (1 << 0)

#       define DACx_AUTODETECT_INT_ENABLE                 (1 << 16)



#define DC_HOT_PLUG_DETECT1_CONTROL                       0x7d00

#define DC_HOT_PLUG_DETECT2_CONTROL                       0x7d10

#define DC_HOT_PLUG_DETECT3_CONTROL                       0x7d24

#       define DC_HOT_PLUG_DETECTx_EN                     (1 << 0)



#define DC_HOT_PLUG_DETECT1_INT_STATUS                    0x7d04

#define DC_HOT_PLUG_DETECT2_INT_STATUS                    0x7d14

#define DC_HOT_PLUG_DETECT3_INT_STATUS                    0x7d28

#       define DC_HOT_PLUG_DETECTx_INT_STATUS             (1 << 0)

#       define DC_HOT_PLUG_DETECTx_SENSE                  (1 << 1)



/* DCE 3.0 */

#define DC_HPD1_INT_STATUS                                0x7d00

#define DC_HPD2_INT_STATUS                                0x7d0c

#define DC_HPD3_INT_STATUS                                0x7d18

#define DC_HPD4_INT_STATUS                                0x7d24

/* DCE 3.2 */

#define DC_HPD5_INT_STATUS                                0x7dc0

#define DC_HPD6_INT_STATUS                                0x7df4

#       define DC_HPDx_INT_STATUS                         (1 << 0)

#       define DC_HPDx_SENSE                              (1 << 1)

#       define DC_HPDx_RX_INT_STATUS                      (1 << 8)



#define DC_HOT_PLUG_DETECT1_INT_CONTROL                   0x7d08

#define DC_HOT_PLUG_DETECT2_INT_CONTROL                   0x7d18

#define DC_HOT_PLUG_DETECT3_INT_CONTROL                   0x7d2c

#       define DC_HOT_PLUG_DETECTx_INT_ACK                (1 << 0)

#       define DC_HOT_PLUG_DETECTx_INT_POLARITY           (1 << 8)

#       define DC_HOT_PLUG_DETECTx_INT_EN                 (1 << 16)

/* DCE 3.2 */

/* DCE 3.0 */

#define DC_HPD1_INT_CONTROL                               0x7d04

#define DC_HPD2_INT_CONTROL                               0x7d10

#define DC_HPD3_INT_CONTROL                               0x7d1c

#define DC_HPD4_INT_CONTROL                               0x7d28

/* DCE 3.2 */

#define DC_HPD5_INT_CONTROL                               0x7dc4

#define DC_HPD6_INT_CONTROL                               0x7df8

#       define DC_HPDx_INT_ACK                            (1 << 0)

#       define DC_HPDx_INT_POLARITY                       (1 << 8)

#       define DC_HPDx_INT_EN                             (1 << 16)

#       define DC_HPDx_RX_INT_ACK                         (1 << 20)

#       define DC_HPDx_RX_INT_EN                          (1 << 24)



/* DCE 3.0 */

#define DC_HPD1_CONTROL                                   0x7d08

#define DC_HPD2_CONTROL                                   0x7d14

#define DC_HPD3_CONTROL                                   0x7d20

#define DC_HPD4_CONTROL                                   0x7d2c

/* DCE 3.2 */

#define DC_HPD5_CONTROL                                   0x7dc8

#define DC_HPD6_CONTROL                                   0x7dfc

#       define DC_HPDx_CONNECTION_TIMER(x)                ((x) << 0)

#       define DC_HPDx_RX_INT_TIMER(x)                    ((x) << 16)

/* DCE 3.2 */

#       define DC_HPDx_EN                                 (1 << 28)



/*

 * PM4

 */

drivers/gpu/drm/radeon/radeon.h

+2 −0
Original line number Diff line number Diff line
@@ -339,6 +339,8 @@ struct radeon_irq { 
	bool		sw_int;

	/* FIXME: use a define max crtc rather than hardcode it */

	bool		crtc_vblank_int[2];

	/* FIXME: use defines for max hpd/dacs */

	bool            hpd[6];

	spinlock_t sw_lock;

	int sw_refcount;

};

drivers/gpu/drm/radeon/radeon_reg.h

+9 −0
Original line number Diff line number Diff line
@@ -887,6 +887,7 @@ 
#       define RADEON_FP_PANEL_FORMAT          (1 <<  3)

#       define RADEON_FP_EN_TMDS               (1 <<  7)

#       define RADEON_FP_DETECT_SENSE          (1 <<  8)

#       define RADEON_FP_DETECT_INT_POL        (1 <<  9)

#       define R200_FP_SOURCE_SEL_MASK         (3 <<  10)

#       define R200_FP_SOURCE_SEL_CRTC1        (0 <<  10)

#       define R200_FP_SOURCE_SEL_CRTC2        (1 <<  10)
@@ -894,6 +895,7 @@ 
#       define R200_FP_SOURCE_SEL_TRANS        (3 <<  10)

#       define RADEON_FP_SEL_CRTC1             (0 << 13)

#       define RADEON_FP_SEL_CRTC2             (1 << 13)

#       define R300_HPD_SEL(x)                 ((x) << 13)

#       define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15)

#       define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16)

#       define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17)
@@ -909,6 +911,7 @@ 
#       define RADEON_FP2_ON                   (1 <<  2)

#       define RADEON_FP2_PANEL_FORMAT         (1 <<  3)

#       define RADEON_FP2_DETECT_SENSE         (1 <<  8)

#       define RADEON_FP2_DETECT_INT_POL       (1 <<  9)

#       define R200_FP2_SOURCE_SEL_MASK        (3 << 10)

#       define R200_FP2_SOURCE_SEL_CRTC1       (0 << 10)

#       define R200_FP2_SOURCE_SEL_CRTC2       (1 << 10)
@@ -988,14 +991,20 @@ 


#define RADEON_GEN_INT_CNTL                 0x0040

#	define RADEON_CRTC_VBLANK_MASK		(1 << 0)

#	define RADEON_FP_DETECT_MASK		(1 << 4)

#	define RADEON_CRTC2_VBLANK_MASK		(1 << 9)

#	define RADEON_FP2_DETECT_MASK		(1 << 10)

#	define RADEON_SW_INT_ENABLE		(1 << 25)

#define RADEON_GEN_INT_STATUS               0x0044

#	define AVIVO_DISPLAY_INT_STATUS		(1 << 0)

#	define RADEON_CRTC_VBLANK_STAT		(1 << 0)

#	define RADEON_CRTC_VBLANK_STAT_ACK	(1 << 0)

#	define RADEON_FP_DETECT_STAT		(1 << 4)

#	define RADEON_FP_DETECT_STAT_ACK	(1 << 4)

#	define RADEON_CRTC2_VBLANK_STAT		(1 << 9)

#	define RADEON_CRTC2_VBLANK_STAT_ACK	(1 << 9)

#	define RADEON_FP2_DETECT_STAT		(1 << 10)

#	define RADEON_FP2_DETECT_STAT_ACK	(1 << 10)

#	define RADEON_SW_INT_FIRE		(1 << 26)

#	define RADEON_SW_INT_TEST		(1 << 25)

#	define RADEON_SW_INT_TEST_ACK		(1 << 25)

drivers/gpu/drm/radeon/rs600d.h

+90 −22
Original line number Diff line number Diff line
@@ -30,27 +30,12 @@ 


/* Registers */

#define R_000040_GEN_INT_CNTL                        0x000040

#define   S_000040_DISPLAY_INT_STATUS(x)               (((x) & 0x1) << 0)

#define   G_000040_DISPLAY_INT_STATUS(x)               (((x) >> 0) & 0x1)

#define   C_000040_DISPLAY_INT_STATUS                  0xFFFFFFFE

#define   S_000040_DMA_VIPH0_INT_EN(x)                 (((x) & 0x1) << 12)

#define   G_000040_DMA_VIPH0_INT_EN(x)                 (((x) >> 12) & 0x1)

#define   C_000040_DMA_VIPH0_INT_EN                    0xFFFFEFFF

#define   S_000040_CRTC2_VSYNC(x)                      (((x) & 0x1) << 6)

#define   G_000040_CRTC2_VSYNC(x)                      (((x) >> 6) & 0x1)

#define   C_000040_CRTC2_VSYNC                         0xFFFFFFBF

#define   S_000040_SNAPSHOT2(x)                        (((x) & 0x1) << 7)

#define   G_000040_SNAPSHOT2(x)                        (((x) >> 7) & 0x1)

#define   C_000040_SNAPSHOT2                           0xFFFFFF7F

#define   S_000040_CRTC2_VBLANK(x)                     (((x) & 0x1) << 9)

#define   G_000040_CRTC2_VBLANK(x)                     (((x) >> 9) & 0x1)

#define   C_000040_CRTC2_VBLANK                        0xFFFFFDFF

#define   S_000040_FP2_DETECT(x)                       (((x) & 0x1) << 10)

#define   G_000040_FP2_DETECT(x)                       (((x) >> 10) & 0x1)

#define   C_000040_FP2_DETECT                          0xFFFFFBFF

#define   S_000040_VSYNC_DIFF_OVER_LIMIT(x)            (((x) & 0x1) << 11)

#define   G_000040_VSYNC_DIFF_OVER_LIMIT(x)            (((x) >> 11) & 0x1)

#define   C_000040_VSYNC_DIFF_OVER_LIMIT               0xFFFFF7FF

#define   S_000040_SCRATCH_INT_MASK(x)                 (((x) & 0x1) << 18)

#define   G_000040_SCRATCH_INT_MASK(x)                 (((x) >> 18) & 0x1)

#define   C_000040_SCRATCH_INT_MASK                    0xFFFBFFFF

#define   S_000040_GUI_IDLE_MASK(x)                    (((x) & 0x1) << 19)

#define   G_000040_GUI_IDLE_MASK(x)                    (((x) >> 19) & 0x1)

#define   C_000040_GUI_IDLE_MASK                       0xFFF7FFFF

#define   S_000040_DMA_VIPH1_INT_EN(x)                 (((x) & 0x1) << 13)

#define   G_000040_DMA_VIPH1_INT_EN(x)                 (((x) >> 13) & 0x1)

#define   C_000040_DMA_VIPH1_INT_EN                    0xFFFFDFFF
@@ -370,7 +355,90 @@ 
#define   S_007EDC_LB_D2_VBLANK_INTERRUPT(x)           (((x) & 0x1) << 5)

#define   G_007EDC_LB_D2_VBLANK_INTERRUPT(x)           (((x) >> 5) & 0x1)

#define   C_007EDC_LB_D2_VBLANK_INTERRUPT              0xFFFFFFDF



#define   S_007EDC_DACA_AUTODETECT_INTERRUPT(x)        (((x) & 0x1) << 16)

#define   G_007EDC_DACA_AUTODETECT_INTERRUPT(x)        (((x) >> 16) & 0x1)

#define   C_007EDC_DACA_AUTODETECT_INTERRUPT           0xFFFEFFFF

#define   S_007EDC_DACB_AUTODETECT_INTERRUPT(x)        (((x) & 0x1) << 17)

#define   G_007EDC_DACB_AUTODETECT_INTERRUPT(x)        (((x) >> 17) & 0x1)

#define   C_007EDC_DACB_AUTODETECT_INTERRUPT           0xFFFDFFFF

#define   S_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(x)    (((x) & 0x1) << 18)

#define   G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(x)    (((x) >> 18) & 0x1)

#define   C_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT       0xFFFBFFFF

#define   S_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(x)    (((x) & 0x1) << 19)

#define   G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(x)    (((x) >> 19) & 0x1)

#define   C_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT       0xFFF7FFFF

#define R_007828_DACA_AUTODETECT_CONTROL               0x007828

#define   S_007828_DACA_AUTODETECT_MODE(x)             (((x) & 0x3) << 0)

#define   G_007828_DACA_AUTODETECT_MODE(x)             (((x) >> 0) & 0x3)

#define   C_007828_DACA_AUTODETECT_MODE                0xFFFFFFFC

#define   S_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) & 0xff) << 8)

#define   G_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) >> 8) & 0xff)

#define   C_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER  0xFFFF00FF

#define   S_007828_DACA_AUTODETECT_CHECK_MASK(x)       (((x) & 0x3) << 16)

#define   G_007828_DACA_AUTODETECT_CHECK_MASK(x)       (((x) >> 16) & 0x3)

#define   C_007828_DACA_AUTODETECT_CHECK_MASK          0xFFFCFFFF

#define R_007838_DACA_AUTODETECT_INT_CONTROL           0x007838

#define   S_007838_DACA_AUTODETECT_ACK(x)              (((x) & 0x1) << 0)

#define   C_007838_DACA_DACA_AUTODETECT_ACK            0xFFFFFFFE

#define   S_007838_DACA_AUTODETECT_INT_ENABLE(x)       (((x) & 0x1) << 16)

#define   G_007838_DACA_AUTODETECT_INT_ENABLE(x)       (((x) >> 16) & 0x1)

#define   C_007838_DACA_AUTODETECT_INT_ENABLE          0xFFFCFFFF

#define R_007A28_DACB_AUTODETECT_CONTROL               0x007A28

#define   S_007A28_DACB_AUTODETECT_MODE(x)             (((x) & 0x3) << 0)

#define   G_007A28_DACB_AUTODETECT_MODE(x)             (((x) >> 0) & 0x3)

#define   C_007A28_DACB_AUTODETECT_MODE                0xFFFFFFFC

#define   S_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) & 0xff) << 8)

#define   G_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) >> 8) & 0xff)

#define   C_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER  0xFFFF00FF

#define   S_007A28_DACB_AUTODETECT_CHECK_MASK(x)       (((x) & 0x3) << 16)

#define   G_007A28_DACB_AUTODETECT_CHECK_MASK(x)       (((x) >> 16) & 0x3)

#define   C_007A28_DACB_AUTODETECT_CHECK_MASK          0xFFFCFFFF

#define R_007A38_DACB_AUTODETECT_INT_CONTROL           0x007A38

#define   S_007A38_DACB_AUTODETECT_ACK(x)              (((x) & 0x1) << 0)

#define   C_007A38_DACB_DACA_AUTODETECT_ACK            0xFFFFFFFE

#define   S_007A38_DACB_AUTODETECT_INT_ENABLE(x)       (((x) & 0x1) << 16)

#define   G_007A38_DACB_AUTODETECT_INT_ENABLE(x)       (((x) >> 16) & 0x1)

#define   C_007A38_DACB_AUTODETECT_INT_ENABLE          0xFFFCFFFF

#define R_007D00_DC_HOT_PLUG_DETECT1_CONTROL           0x007D00

#define   S_007D00_DC_HOT_PLUG_DETECT1_EN(x)           (((x) & 0x1) << 0)

#define   G_007D00_DC_HOT_PLUG_DETECT1_EN(x)           (((x) >> 0) & 0x1)

#define   C_007D00_DC_HOT_PLUG_DETECT1_EN              0xFFFFFFFE

#define R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS        0x007D04

#define   S_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS(x)   (((x) & 0x1) << 0)

#define   G_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS(x)   (((x) >> 0) & 0x1)

#define   C_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS      0xFFFFFFFE

#define   S_007D04_DC_HOT_PLUG_DETECT1_SENSE(x)        (((x) & 0x1) << 1)

#define   G_007D04_DC_HOT_PLUG_DETECT1_SENSE(x)        (((x) >> 1) & 0x1)

#define   C_007D04_DC_HOT_PLUG_DETECT1_SENSE           0xFFFFFFFD

#define R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL       0x007D08

#define   S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(x)      (((x) & 0x1) << 0)

#define   C_007D08_DC_HOT_PLUG_DETECT1_INT_ACK         0xFFFFFFFE

#define   S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(x) (((x) & 0x1) << 8)

#define   G_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(x) (((x) >> 8) & 0x1)

#define   C_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY    0xFFFFFEFF

#define   S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(x)       (((x) & 0x1) << 16)

#define   G_007D08_DC_HOT_PLUG_DETECT1_INT_EN(x)       (((x) >> 16) & 0x1)

#define   C_007D08_DC_HOT_PLUG_DETECT1_INT_EN          0xFFFEFFFF

#define R_007D10_DC_HOT_PLUG_DETECT2_CONTROL           0x007D10

#define   S_007D10_DC_HOT_PLUG_DETECT2_EN(x)           (((x) & 0x1) << 0)

#define   G_007D10_DC_HOT_PLUG_DETECT2_EN(x)           (((x) >> 0) & 0x1)

#define   C_007D10_DC_HOT_PLUG_DETECT2_EN              0xFFFFFFFE

#define R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS        0x007D14

#define   S_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS(x)   (((x) & 0x1) << 0)

#define   G_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS(x)   (((x) >> 0) & 0x1)

#define   C_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS      0xFFFFFFFE

#define   S_007D14_DC_HOT_PLUG_DETECT2_SENSE(x)        (((x) & 0x1) << 1)

#define   G_007D14_DC_HOT_PLUG_DETECT2_SENSE(x)        (((x) >> 1) & 0x1)

#define   C_007D14_DC_HOT_PLUG_DETECT2_SENSE           0xFFFFFFFD

#define R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL       0x007D18

#define   S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(x)      (((x) & 0x1) << 0)

#define   C_007D18_DC_HOT_PLUG_DETECT2_INT_ACK         0xFFFFFFFE

#define   S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(x) (((x) & 0x1) << 8)

#define   G_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(x) (((x) >> 8) & 0x1)

#define   C_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY    0xFFFFFEFF

#define   S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(x)       (((x) & 0x1) << 16)

#define   G_007D18_DC_HOT_PLUG_DETECT2_INT_EN(x)       (((x) >> 16) & 0x1)

#define   C_007D18_DC_HOT_PLUG_DETECT2_INT_EN          0xFFFEFFFF



/* MC registers */

#define R_000000_MC_STATUS                           0x000000