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Commit b4c95b24 authored by Dhaval Patel's avatar Dhaval Patel
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ARM: dts: msm: add mdss smmu register range for msm8996 



Add mdss smmu context bank register range for
msm8996 target.

Change-Id: I863f7e57cce9fa12e0d8a603ac50c42775d62414
Signed-off-by: default avatarDhaval Patel <pdhaval@codeaurora.org>
parent 0fdb29e6
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