Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit b478491f authored by David Howells's avatar David Howells
Browse files

MN10300: Allow some cacheflushes to be avoided if cache snooping is available 



The AM34 core is able to do cache snooping, and so can skip some of the cache
flushing.

Signed-off-by: default avatarDavid Howells <dhowells@redhat.com>
parent 9731d237

arch/mn10300/Kconfig

+1 −0
Original line number Original line Diff line number Diff line
@@ -18,6 +18,7 @@ config AM33_3 
config AM34_2

config AM34_2

	def_bool n

	def_bool n

	select MN10300_HAS_ATOMIC_OPS_UNIT

	select MN10300_HAS_ATOMIC_OPS_UNIT

	select MN10300_HAS_CACHE_SNOOP





config MMU

config MMU

	def_bool y

	def_bool y

arch/mn10300/include/asm/cacheflush.h

+10 −6
Original line number Original line Diff line number Diff line
@@ -131,18 +131,22 @@ extern void mn10300_dcache_flush_inv_range2(unsigned long start, unsigned long s 
/*

/*

 * Physically-indexed cache management

 * Physically-indexed cache management

 */

 */

#ifdef CONFIG_MN10300_CACHE_ENABLED

#if defined(CONFIG_MN10300_CACHE_FLUSH_ICACHE)



extern void flush_icache_page(struct vm_area_struct *vma, struct page *page);

extern void flush_icache_range(unsigned long start, unsigned long end);

#elif defined(CONFIG_MN10300_CACHE_INV_ICACHE)

static inline void flush_icache_page(struct vm_area_struct *vma,

				     struct page *page)

{

	mn10300_icache_inv_page(page_to_phys(page));

}

extern void flush_icache_range(unsigned long start, unsigned long end);

extern void flush_icache_range(unsigned long start, unsigned long end);

extern void flush_icache_page(struct vm_area_struct *vma, struct page *pg);



#else

#else



#define flush_icache_range(start, end)		do {} while (0)

#define flush_icache_range(start, end)		do {} while (0)

#define flush_icache_page(vma, pg)		do {} while (0)

#define flush_icache_page(vma, pg)		do {} while (0)



#endif

#endif







#define flush_icache_user_range(vma, pg, adr, len) \

#define flush_icache_user_range(vma, pg, adr, len) \

	flush_icache_range(adr, adr + len)

	flush_icache_range(adr, adr + len)

arch/mn10300/kernel/kprobes.c

+4 −0
Original line number Original line Diff line number Diff line
@@ -377,8 +377,10 @@ void __kprobes arch_arm_kprobe(struct kprobe *p) 




void __kprobes arch_disarm_kprobe(struct kprobe *p)

void __kprobes arch_disarm_kprobe(struct kprobe *p)

{

{

#ifndef CONFIG_MN10300_CACHE_SNOOP

	mn10300_dcache_flush();

	mn10300_dcache_flush();

	mn10300_icache_inv();

	mn10300_icache_inv();

#endif

}

}





void arch_remove_kprobe(struct kprobe *p)

void arch_remove_kprobe(struct kprobe *p)
@@ -390,8 +392,10 @@ void __kprobes disarm_kprobe(struct kprobe *p, struct pt_regs *regs) 
{

{

	*p->addr = p->opcode;

	*p->addr = p->opcode;

	regs->pc = (unsigned long) p->addr;

	regs->pc = (unsigned long) p->addr;

#ifndef CONFIG_MN10300_CACHE_SNOOP

	mn10300_dcache_flush();

	mn10300_dcache_flush();

	mn10300_icache_inv();

	mn10300_icache_inv();

#endif

}

}





static inline

static inline

arch/mn10300/kernel/traps.c

+2 −0
Original line number Original line Diff line number Diff line
@@ -533,8 +533,10 @@ void __init set_intr_stub(enum exception_code code, void *handler) 
	vector[6] = 0xcb;

	vector[6] = 0xcb;

	vector[7] = 0xcb;

	vector[7] = 0xcb;





#ifndef CONFIG_MN10300_CACHE_SNOOP

	mn10300_dcache_flush_inv();

	mn10300_dcache_flush_inv();

	mn10300_icache_inv();

	mn10300_icache_inv();

#endif

}

}





/*

/*

arch/mn10300/mm/Kconfig.cache

+34 −0
Original line number Original line Diff line number Diff line
@@ -22,12 +22,26 @@ choice 




config MN10300_CACHE_WBACK

config MN10300_CACHE_WBACK

	bool "Write-Back"

	bool "Write-Back"

	help

	  The dcache operates in delayed write-back mode.  It must be manually

	  flushed if writes are made that subsequently need to be executed or

	  to be DMA'd by a device.





config MN10300_CACHE_WTHRU

config MN10300_CACHE_WTHRU

	bool "Write-Through"

	bool "Write-Through"

	help

	  The dcache operates in immediate write-through mode.  Writes are

	  committed to RAM immediately in addition to being stored in the

	  cache.  This means that the written data is immediately available for

	  execution or DMA.



	  This is not available for use with an SMP kernel if cache flushing

	  and invalidation by automatic purge register is not selected.





config MN10300_CACHE_DISABLED

config MN10300_CACHE_DISABLED

	bool "Disabled"

	bool "Disabled"

	help

	  The icache and dcache are disabled.





endchoice

endchoice
@@ -64,3 +78,23 @@ config MN10300_CACHE_FLUSH_BY_TAG 




config MN10300_CACHE_FLUSH_BY_REG

config MN10300_CACHE_FLUSH_BY_REG

	def_bool y if MN10300_CACHE_MANAGE_BY_REG && MN10300_CACHE_WBACK

	def_bool y if MN10300_CACHE_MANAGE_BY_REG && MN10300_CACHE_WBACK





config MN10300_HAS_CACHE_SNOOP

	def_bool n



config MN10300_CACHE_SNOOP

	bool "Use CPU Cache Snooping"

	depends on MN10300_CACHE_ENABLED && MN10300_HAS_CACHE_SNOOP

	default y



config MN10300_CACHE_FLUSH_ICACHE

	def_bool y if MN10300_CACHE_WBACK && !MN10300_CACHE_SNOOP

	help

	  Set if we need the dcache flushing before the icache is invalidated.



config MN10300_CACHE_INV_ICACHE

	def_bool y if MN10300_CACHE_WTHRU && !MN10300_CACHE_SNOOP

	help

	  Set if we need the icache to be invalidated, even if the dcache is in

	  write-through mode and doesn't need flushing.