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Commit b44a53d1 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6 

* 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6:
  drm: index i shadowed in 2nd loop
  drm/nv50-nvc0: prevent multiple vm/bar flushes occuring simultanenously
  drm/nouveau: fix regression causing ttm to not be able to evict vram
  drm/i915: Rebind the buffer if its alignment constraints changes with tiling
  drm/i915: Disable GPU semaphores by default
  drm/i915: Do not overflow the MMADDR write FIFO
  Revert "drm/i915: fix corruptions on i8xx due to relaxed fencing"
parents 214d93b0 062ac622

drivers/gpu/drm/drm_fb_helper.c

+2 −2
Original line number Diff line number Diff line
@@ -672,7 +672,7 @@ int drm_fb_helper_setcmap(struct fb_cmap *cmap, struct fb_info *info) 
	struct drm_crtc_helper_funcs *crtc_funcs;

	u16 *red, *green, *blue, *transp;

	struct drm_crtc *crtc;

	int i, rc = 0;

	int i, j, rc = 0;

	int start;



	for (i = 0; i < fb_helper->crtc_count; i++) {
@@ -685,7 +685,7 @@ int drm_fb_helper_setcmap(struct fb_cmap *cmap, struct fb_info *info) 
		transp = cmap->transp;

		start = cmap->start;



		for (i = 0; i < cmap->len; i++) {

		for (j = 0; j < cmap->len; j++) {

			u16 hred, hgreen, hblue, htransp = 0xffff;



			hred = *red++;

drivers/gpu/drm/i915/i915_debugfs.c

+2 −2
Original line number Diff line number Diff line
@@ -865,7 +865,7 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused) 
		int max_freq;



		/* RPSTAT1 is in the GT power well */

		__gen6_force_wake_get(dev_priv);

		__gen6_gt_force_wake_get(dev_priv);



		seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);

		seq_printf(m, "RPSTAT1: 0x%08x\n", I915_READ(GEN6_RPSTAT1));
@@ -888,7 +888,7 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused) 
		seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",

			   max_freq * 100);



		__gen6_force_wake_put(dev_priv);

		__gen6_gt_force_wake_put(dev_priv);

	} else {

		seq_printf(m, "no P-state info available\n");

	}

drivers/gpu/drm/i915/i915_drv.c

+15 −2
Original line number Diff line number Diff line
@@ -46,6 +46,9 @@ module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400); 
unsigned int i915_powersave = 1;

module_param_named(powersave, i915_powersave, int, 0600);



unsigned int i915_semaphores = 0;

module_param_named(semaphores, i915_semaphores, int, 0600);



unsigned int i915_enable_rc6 = 0;

module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
@@ -254,7 +257,7 @@ void intel_detect_pch (struct drm_device *dev) 
	}

}



void __gen6_force_wake_get(struct drm_i915_private *dev_priv)

void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)

{

	int count;
@@ -270,12 +273,22 @@ void __gen6_force_wake_get(struct drm_i915_private *dev_priv) 
		udelay(10);

}



void __gen6_force_wake_put(struct drm_i915_private *dev_priv)

void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)

{

	I915_WRITE_NOTRACE(FORCEWAKE, 0);

	POSTING_READ(FORCEWAKE);

}



void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)

{

	int loop = 500;

	u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);

	while (fifo < 20 && loop--) {

		udelay(10);

		fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);

	}

}



static int i915_drm_freeze(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

drivers/gpu/drm/i915/i915_drv.h

+19 −5
Original line number Diff line number Diff line
@@ -956,6 +956,7 @@ extern struct drm_ioctl_desc i915_ioctls[]; 
extern int i915_max_ioctl;

extern unsigned int i915_fbpercrtc;

extern unsigned int i915_powersave;

extern unsigned int i915_semaphores;

extern unsigned int i915_lvds_downclock;

extern unsigned int i915_panel_use_ssc;

extern unsigned int i915_enable_rc6;
@@ -1177,6 +1178,9 @@ void i915_gem_detach_phys_object(struct drm_device *dev, 
void i915_gem_free_all_phys_object(struct drm_device *dev);

void i915_gem_release(struct drm_device *dev, struct drm_file *file);



uint32_t

i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj);



/* i915_gem_gtt.c */

void i915_gem_restore_gtt_mappings(struct drm_device *dev);

int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj);
@@ -1353,22 +1357,32 @@ __i915_write(64, q) 
 * must be set to prevent GT core from power down and stale values being

 * returned.

 */

void __gen6_force_wake_get(struct drm_i915_private *dev_priv);

void __gen6_force_wake_put (struct drm_i915_private *dev_priv);

static inline u32 i915_safe_read(struct drm_i915_private *dev_priv, u32 reg)

void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);

void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);

void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);



static inline u32 i915_gt_read(struct drm_i915_private *dev_priv, u32 reg)

{

	u32 val;



	if (dev_priv->info->gen >= 6) {

		__gen6_force_wake_get(dev_priv);

		__gen6_gt_force_wake_get(dev_priv);

		val = I915_READ(reg);

		__gen6_force_wake_put(dev_priv);

		__gen6_gt_force_wake_put(dev_priv);

	} else

		val = I915_READ(reg);



	return val;

}



static inline void i915_gt_write(struct drm_i915_private *dev_priv,

				u32 reg, u32 val)

{

	if (dev_priv->info->gen >= 6)

		__gen6_gt_wait_for_fifo(dev_priv);

	I915_WRITE(reg, val);

}



static inline void

i915_write(struct drm_i915_private *dev_priv, u32 reg, u64 val, int len)

{

drivers/gpu/drm/i915/i915_gem.c

+1 −1
Original line number Diff line number Diff line
@@ -1398,7 +1398,7 @@ i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj) 
 * Return the required GTT alignment for an object, only taking into account

 * unfenced tiled surface requirements.

 */

static uint32_t

uint32_t

i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj)

{

	struct drm_device *dev = obj->base.dev;