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Commit b3fdec35 authored by Archana Sathyakumar's avatar Archana Sathyakumar Committed by Matt Wagantall
Browse files

ARM: dts: msm: Support energy-aware feature for msm8996 



Add EA node for msm8996 target.

Change-Id: I6b2c334b4441e170a5e74ae8fb9ca4d695cdea2e
Signed-off-by: default avatarArchana Sathyakumar <asathyak@codeaurora.org>
parent 4ff9f6ea

arch/arm/boot/dts/qcom/msm8996.dtsi

+28 −0
Original line number Diff line number Diff line
@@ -53,6 +53,7 @@ 
			qcom,cpuss-csr = <&cpuss_csr>;

			qcom,acc = <&acc0>;

			qcom,sleep-status = <&cpu0_slp_sts>;

			qcom,ea = <&ea0>;

			next-level-cache = <&L2_0>;

			L2_0: l2-cache {

			      compatible = "arm,arch-cache";
@@ -69,6 +70,7 @@ 
			enable-method = "qcom,msm8996-acc";

			qcom,acc = <&acc1>;

			qcom,sleep-status = <&cpu1_slp_sts>;

			qcom,ea = <&ea1>;

			next-level-cache = <&L2_0>;

		};
@@ -79,6 +81,7 @@ 
			enable-method = "qcom,msm8996-acc";

			qcom,acc = <&acc2>;

			qcom,sleep-status = <&cpu2_slp_sts>;

			qcom,ea = <&ea2>;

			next-level-cache = <&L2_1>;

			L2_1: l2-cache {

			      compatible = "arm,arch-cache";
@@ -94,6 +97,7 @@ 
			enable-method = "qcom,msm8996-acc";

			qcom,sleep-status = <&cpu3_slp_sts>;

			qcom,acc = <&acc3>;

			qcom,ea = <&ea3>;

			next-level-cache = <&L2_1>;

		};
@@ -2690,6 +2694,30 @@ 
		};

	};



	qcom,msm-core@70000 {

		compatible = "qcom,apss-core-ea";

		reg = <0x70000 0x1000>;

		qcom,low-hyst-temp = <10>;

		qcom,high-hyst-temp = <5>;

		qcom,polling-interval = <50>;



		ea0: ea0 {

			sensor = <&sensor_information4>;

		};



		ea1: ea1 {

			sensor = <&sensor_information6>;

		};



		ea2: ea2 {

			sensor = <&sensor_information9>;

		};



		ea3: ea3 {

			sensor = <&sensor_information11>;

		};

	};



	qcom_tzlog: tz-log@66bf720 {

		compatible = "qcom,tz-log";

		reg = <0x066bf720 0x2000>;