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Commit b3f9ad93 authored by Michel Thierry's avatar Michel Thierry Committed by Daniel Vetter
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drm/i915/bdw: 3D_CHICKEN3 has write mask bits 



The workaround to limit SDE poly depth FIFO to 2 is not applied because
3D Chicken-3 mask bit is not set.

WaLimitSizeOfSDEPolyFifo is only for BDW-A and could be removed.

Signed-off-by: default avatarMichel Thierry <michel.thierry@intel.com>
Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent a7de62fe

drivers/gpu/drm/i915/intel_pm.c

+1 −1
Original line number Diff line number Diff line
@@ -5375,7 +5375,7 @@ static void gen8_init_clock_gating(struct drm_device *dev) 
	I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));



	I915_WRITE(_3D_CHICKEN3,

		   _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));

		   _MASKED_BIT_ENABLE(_3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2)));



	I915_WRITE(COMMON_SLICE_CHICKEN2,

		   _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));