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Commit b315fedf authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
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drm/i915: Kill IRONLAKE_FDI_FREQ check 



ironlake_fdi_compute_config() already checks that we have enough
FDI bandwidth. And it doesn't just use a hardcoded value but takes
into account factors such as the actual FDI frequency, shared FDI
B/C lanes, etc.

Suggested-by: default avatarDaniel Vetter <daniel@ffwll.ch>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 65ce4bf5

drivers/gpu/drm/i915/intel_display.c

+0 −10
Original line number Original line Diff line number Diff line
@@ -69,9 +69,6 @@ struct intel_limit { 
	intel_p2_t	    p2;

	intel_p2_t	    p2;

};

};





/* FDI */

#define IRONLAKE_FDI_FREQ		2700000 /* in kHz for mode->clock */



int

int

intel_pch_rawclk(struct drm_device *dev)

intel_pch_rawclk(struct drm_device *dev)

{

{
@@ -4107,13 +4104,6 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, 
	struct drm_device *dev = crtc->base.dev;

	struct drm_device *dev = crtc->base.dev;

	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;

	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;





	if (HAS_PCH_SPLIT(dev)) {

		/* FDI link clock is fixed at 2.7G */

		if (pipe_config->requested_mode.clock * 3

		    > IRONLAKE_FDI_FREQ * 4)

			return -EINVAL;

	}



	/* Cantiga+ cannot handle modes with a hsync front porch of 0.

	/* Cantiga+ cannot handle modes with a hsync front porch of 0.

	 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.

	 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.

	 */

	 */