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Commit b2ceddfa authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

radeon: add RS400 family support. 



This adds support for the RS400 family of IGPs for Intel CPUs.

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent f0738e92

drivers/gpu/drm/radeon/radeon_cp.c

+4 −2
Original line number Diff line number Diff line
@@ -133,9 +133,10 @@ static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base) 
	} else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {

		R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);

		R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);

	} else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480) {

	} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||

		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {

		RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);

		RADEON_WRITE(RS480_AGP_BASE_2, 0);

		RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);

	} else {

		RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);

		if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
@@ -352,6 +353,7 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) 
		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||

		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||

		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||

		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||

		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {

		DRM_INFO("Loading R300 Microcode\n");

		for (i = 0; i < 256; i++) {

drivers/gpu/drm/radeon/radeon_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -123,6 +123,7 @@ enum radeon_family { 
	CHIP_RV380,

	CHIP_R420,

	CHIP_RV410,

	CHIP_RS400,

	CHIP_RS480,

	CHIP_RS690,

	CHIP_RS740,

include/drm/drm_pciids.h

+4 −2
Original line number Diff line number Diff line
@@ -113,8 +113,10 @@ 
	{0x1002, 0x5964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \

	{0x1002, 0x5965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \

	{0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \

	{0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \

	{0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \

	{0x1002, 0x5a41, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_IGPGART}, \

	{0x1002, 0x5a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \

	{0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_IGPGART}, \

	{0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \

	{0x1002, 0x5b60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5b62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x5b63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \