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Commit b2b964f0 authored by Divy Le Ray's avatar Divy Le Ray Committed by David S. Miller
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cxgb3: prefetch buffer access in GRO mode 



Elmininate a cache miss when accessing the CPL header within
the first aggregated buffer.

Signed-off-by: default avatarDivy Le Ray <divy@chelsio.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 8f435804

drivers/net/cxgb3/sge.c

+3 −0
Original line number Diff line number Diff line
@@ -2029,6 +2029,8 @@ static void lro_add_page(struct adapter *adap, struct sge_qset *qs, 
	pci_unmap_single(adap->pdev, pci_unmap_addr(sd, dma_addr),

			 fl->buf_size, PCI_DMA_FROMDEVICE);



	prefetch(&qs->lro_frag_tbl);



	rx_frag += nr_frags;

	rx_frag->page = sd->pg_chunk.page;

	rx_frag->page_offset = sd->pg_chunk.offset + offset;
@@ -2997,6 +2999,7 @@ int t3_sge_alloc_qset(struct adapter *adapter, unsigned int id, int nports, 
		     V_NEWTIMER(q->rspq.holdoff_tmr));



	mod_timer(&q->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD);



	return 0;



err_unlock: