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Commit b20c99eb authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'x86-ras-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 RAS changes from Ingo Molnar:
 "[ The reason for drivers/ updates is that Boris asked for the
    drivers/edac/ changes to go via x86/ras in this cycle ]

  Main changes:

   - AMD CPUs:
      . Add ECC event decoding support for new F15h models
      . Various erratum fixes
      . Fix single-channel on dual-channel-controllers bug.

   - Intel CPUs:
      . UC uncorrectable memory error parsing fix
      . Add support for CMC (Corrected Machine Check) 'FF' (Firmware
        First) flag in the APEI HEST

   - Various cleanups and fixes"

* 'x86-ras-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  amd64_edac: Fix incorrect wraparounds
  amd64_edac: Correct erratum 505 range
  cpc925_edac: Use proper array termination
  x86/mce, acpi/apei: Only disable banks listed in HEST if mce is configured
  amd64_edac: Get rid of boot_cpu_data accesses
  amd64_edac: Add ECC decoding support for newer F15h models
  x86, amd_nb: Clarify F15h, model 30h GART and L3 support
  pci_ids: Add PCI device ID functions 3 and 4 for newer F15h models.
  x38_edac: Make a local function static
  i3200_edac: Make a local function static
  x86/mce: Pay no attention to 'F' bit in MCACOD when parsing 'UC' errors
  APEI/ERST: Fix error message formatting
  amd64_edac: Fix single-channel setups
  EDAC: Replace strict_strtol() with kstrtol()
  mce: acpi/apei: Soft-offline a page on firmware GHES notification
  mce: acpi/apei: Add a boot option to disable ff mode for corrected errors
  mce: acpi/apei: Honour Firmware First for MCA banks listed in APEI HEST CMC
parents bb8c4701 ead6fa95

Documentation/x86/x86_64/boot-options.txt

+5 −0
Original line number Diff line number Diff line
@@ -176,6 +176,11 @@ ACPI 


  acpi=noirq	Don't route interrupts



  acpi=nocmcff	Disable firmware first mode for corrected errors. This

		disables parsing the HEST CMC error source to check if

		firmware has set the FF flag. This may result in

		duplicate corrected error reports.



PCI



  pci=off		Don't use PCI

arch/x86/include/asm/acpi.h

+2 −0
Original line number Diff line number Diff line
@@ -86,6 +86,7 @@ extern int acpi_pci_disabled; 
extern int acpi_skip_timer_override;

extern int acpi_use_timer_override;

extern int acpi_fix_pin2_polarity;

extern int acpi_disable_cmcff;



extern u8 acpi_sci_flags;

extern int acpi_sci_override_gsi;
@@ -168,6 +169,7 @@ static inline void arch_acpi_set_pdc_bits(u32 *buf) 


#define acpi_lapic 0

#define acpi_ioapic 0

#define acpi_disable_cmcff 0

static inline void acpi_noirq_set(void) { }

static inline void acpi_disable_pci(void) { }

static inline void disable_acpi(void) { }

arch/x86/include/asm/mce.h

+14 −2
Original line number Diff line number Diff line
@@ -32,11 +32,20 @@ 
#define MCI_STATUS_PCC   (1ULL<<57)  /* processor context corrupt */

#define MCI_STATUS_S	 (1ULL<<56)  /* Signaled machine check */

#define MCI_STATUS_AR	 (1ULL<<55)  /* Action required */

#define MCACOD		  0xffff     /* MCA Error Code */



/*

 * Note that the full MCACOD field of IA32_MCi_STATUS MSR is

 * bits 15:0.  But bit 12 is the 'F' bit, defined for corrected

 * errors to indicate that errors are being filtered by hardware.

 * We should mask out bit 12 when looking for specific signatures

 * of uncorrected errors - so the F bit is deliberately skipped

 * in this #define.

 */

#define MCACOD		  0xefff     /* MCA Error Code */



/* Architecturally defined codes from SDM Vol. 3B Chapter 15 */

#define MCACOD_SCRUB	0x00C0	/* 0xC0-0xCF Memory Scrubbing */

#define MCACOD_SCRUBMSK	0xfff0

#define MCACOD_SCRUBMSK	0xeff0	/* Skip bit 12 ('F' bit) */

#define MCACOD_L3WB	0x017A	/* L3 Explicit Writeback */

#define MCACOD_DATA	0x0134	/* Data Load */

#define MCACOD_INSTR	0x0150	/* Instruction Fetch */
@@ -188,6 +197,9 @@ extern void register_mce_write_callback(ssize_t (*)(struct file *filp, 
				    const char __user *ubuf,

				    size_t usize, loff_t *off));



/* Disable CMCI/polling for MCA bank claimed by firmware */

extern void mce_disable_bank(int bank);



/*

 * Exception handler

 */

arch/x86/kernel/acpi/boot.c

+5 −0
Original line number Diff line number Diff line
@@ -67,6 +67,7 @@ EXPORT_SYMBOL(acpi_pci_disabled); 
int acpi_lapic;

int acpi_ioapic;

int acpi_strict;

int acpi_disable_cmcff;



u8 acpi_sci_flags __initdata;

int acpi_sci_override_gsi __initdata;
@@ -1622,6 +1623,10 @@ static int __init parse_acpi(char *arg) 
	/* "acpi=copy_dsdt" copys DSDT */

	else if (strcmp(arg, "copy_dsdt") == 0) {

		acpi_gbl_copy_dsdt_locally = 1;

	}

	/* "acpi=nocmcff" disables FF mode for corrected errors */

	else if (strcmp(arg, "nocmcff") == 0) {

		acpi_disable_cmcff = 1;

	} else {

		/* Core will printk when we return error. */

		return -EINVAL;

arch/x86/kernel/amd_nb.c

+11 −2
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ const struct pci_device_id amd_nb_misc_ids[] = { 
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },

	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },

	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },

	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },

	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },

	{}

};
@@ -27,6 +28,7 @@ EXPORT_SYMBOL(amd_nb_misc_ids); 


static const struct pci_device_id amd_nb_link_ids[] = {

	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },

	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F4) },

	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },

	{}

};
@@ -83,10 +85,17 @@ int amd_cache_northbridges(void) 
			next_northbridge(link, amd_nb_link_ids);

	}



	/* GART present only on Fam15h upto model 0fh */

	if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10 ||

	    boot_cpu_data.x86 == 0x15)

	    (boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model < 0x10))

		amd_northbridges.flags |= AMD_NB_GART;



	/*

	 * Check for L3 cache presence.

	 */

	if (!cpuid_edx(0x80000006))

		return 0;



	/*

	 * Some CPU families support L3 Cache Index Disable. There are some

	 * limitations because of E382 and E388 on family 0x10.