Loading arch/arm/boot/dts/qcom/mdmcalifornium.dtsi +40 −0 Original line number Diff line number Diff line Loading @@ -211,6 +211,46 @@ qcom,a7ssmux-opp-store-vcorner = <&CPU0>; }; qcom,msm-cpufreq { compatible = "qcom,msm-cpufreq"; clocks = <&clock_cpu clk_a7ssmux>, <&clock_cpu clk_a7ssmux>, <&clock_cpu clk_a7ssmux>, <&clock_cpu clk_a7ssmux>; clock-names = "cpu0_clk", "cpu1_clk", "cpu2_clk", "cpu3_clk"; qcom,cpufreq-table = < 200000 >, < 300000 >, < 384000 >, < 600000 >, < 787200 >, < 998400 >, < 1190400 >, < 1286400 >; }; devfreq-cpufreq { cpubw-cpufreq { target-dev = <&cpubw>; cpu-to-dev-map = < 600000 1541 >, < 787200 3082 >, < 1286400 3952 >; }; }; cpubw: qcom,cpubw { compatible = "qcom,devbw"; governor = "cpufreq"; qcom,src-dst-ports = <1 512>; qcom,active-only; qcom,bw-tbl = < 1541 /* 202 MHz */ >, < 3082 /* 404 MHz */ >, < 3952 /* 518 MHz */ >; }; restart@4ab000 { compatible = "qcom,pshold"; reg = <0x4ab000 0x4>, Loading Loading
arch/arm/boot/dts/qcom/mdmcalifornium.dtsi +40 −0 Original line number Diff line number Diff line Loading @@ -211,6 +211,46 @@ qcom,a7ssmux-opp-store-vcorner = <&CPU0>; }; qcom,msm-cpufreq { compatible = "qcom,msm-cpufreq"; clocks = <&clock_cpu clk_a7ssmux>, <&clock_cpu clk_a7ssmux>, <&clock_cpu clk_a7ssmux>, <&clock_cpu clk_a7ssmux>; clock-names = "cpu0_clk", "cpu1_clk", "cpu2_clk", "cpu3_clk"; qcom,cpufreq-table = < 200000 >, < 300000 >, < 384000 >, < 600000 >, < 787200 >, < 998400 >, < 1190400 >, < 1286400 >; }; devfreq-cpufreq { cpubw-cpufreq { target-dev = <&cpubw>; cpu-to-dev-map = < 600000 1541 >, < 787200 3082 >, < 1286400 3952 >; }; }; cpubw: qcom,cpubw { compatible = "qcom,devbw"; governor = "cpufreq"; qcom,src-dst-ports = <1 512>; qcom,active-only; qcom,bw-tbl = < 1541 /* 202 MHz */ >, < 3082 /* 404 MHz */ >, < 3952 /* 518 MHz */ >; }; restart@4ab000 { compatible = "qcom,pshold"; reg = <0x4ab000 0x4>, Loading