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Commit b1d3d688 authored by Carter Cooper's avatar Carter Cooper
Browse files

msm: kgsl: Rate limit all logs from the interrupt handler 



Ensure that all the logs that can be triggered from the
interrupt handler are rate limited.

CRs-Fixed: 971145
Change-Id: I9fe4a6b28be0dc6299467fb8402bef3694aeac76
Signed-off-by: default avatarCarter Cooper <ccooper@codeaurora.org>
parent ef78af1b

drivers/gpu/msm/adreno.c

+3 −2
Original line number Diff line number Diff line
@@ -692,7 +692,8 @@ void adreno_irqctrl(struct adreno_device *adreno_dev, int state) 
 */

void adreno_hang_int_callback(struct adreno_device *adreno_dev, int bit)

{

	KGSL_DRV_CRIT(KGSL_DEVICE(adreno_dev), "MISC: GPU hang detected\n");

	KGSL_DRV_CRIT_RATELIMIT(KGSL_DEVICE(adreno_dev),

			"MISC: GPU hang detected\n");

	adreno_irqctrl(adreno_dev, 0);



	/* Trigger a fault in the dispatcher - this will effect a restart */
@@ -734,7 +735,7 @@ static irqreturn_t adreno_irq_handler(struct kgsl_device *device) 
			if (irq_params->mask & BIT(i))

				irq_params->funcs[i].func(adreno_dev, i);

		} else

			KGSL_DRV_CRIT(device,

			KGSL_DRV_CRIT_RATELIMIT(device,

					"Unhandled interrupt bit %x\n", i);



		ret = IRQ_HANDLED;

drivers/gpu/msm/adreno_a3xx.c

+4 −5
Original line number Diff line number Diff line
@@ -677,7 +677,7 @@ static void a3xx_err_callback(struct adreno_device *adreno_dev, int bit) 
		 * Return the word address of the erroring register so that it

		 * matches the register specification

		 */

		KGSL_DRV_CRIT(device,

		KGSL_DRV_CRIT_RATELIMIT(device,

			"RBBM | AHB bus error | %s | addr=%x | ports=%x:%x\n",

			reg & (1 << 28) ? "WRITE" : "READ",

			(reg & 0xFFFFF) >> 2, (reg >> 20) & 0x3,
@@ -685,8 +685,7 @@ static void a3xx_err_callback(struct adreno_device *adreno_dev, int bit) 


		/* Clear the error */

		kgsl_regwrite(device, A3XX_RBBM_AHB_CMD, (1 << 3));



		return;

		break;

	}

	case A3XX_INT_RBBM_ATB_BUS_OVERFLOW:

		KGSL_DRV_CRIT_RATELIMIT(device, "RBBM: ATB bus oveflow\n");
@@ -710,11 +709,11 @@ static void a3xx_err_callback(struct adreno_device *adreno_dev, int bit) 
		break;

	case A3XX_INT_CP_REG_PROTECT_FAULT:

		kgsl_regread(device, A3XX_CP_PROTECT_STATUS, &reg);

		KGSL_DRV_CRIT(device,

		KGSL_DRV_CRIT_RATELIMIT(device,

			"CP | Protected mode error| %s | addr=%x\n",

			reg & (1 << 24) ? "WRITE" : "READ",

			(reg & 0xFFFFF) >> 2);

		return;

		break;

	case A3XX_INT_CP_AHB_ERROR_HALT:

		KGSL_DRV_CRIT_RATELIMIT(device,

			"ringbuffer AHB error interrupt\n");

drivers/gpu/msm/adreno_a4xx.c

+4 −4
Original line number Diff line number Diff line
@@ -744,7 +744,7 @@ static void a4xx_err_callback(struct adreno_device *adreno_dev, int bit) 
		 * Return the word address of the erroring register so that it

		 * matches the register specification

		 */

		KGSL_DRV_CRIT(device,

		KGSL_DRV_CRIT_RATELIMIT(device,

			"RBBM | AHB bus error | %s | addr=%x | ports=%x:%x\n",

			reg & (1 << 28) ? "WRITE" : "READ",

			(reg & 0xFFFFF) >> 2, (reg >> 20) & 0x3,
@@ -752,7 +752,7 @@ static void a4xx_err_callback(struct adreno_device *adreno_dev, int bit) 


		/* Clear the error */

		kgsl_regwrite(device, A4XX_RBBM_AHB_CMD, (1 << 4));

		return;

		break;

	}

	case A4XX_INT_RBBM_REG_TIMEOUT:

		KGSL_DRV_CRIT_RATELIMIT(device, "RBBM: AHB register timeout\n");
@@ -798,11 +798,11 @@ static void a4xx_err_callback(struct adreno_device *adreno_dev, int bit) 
	}

	case A4XX_INT_CP_REG_PROTECT_FAULT:

		kgsl_regread(device, A4XX_CP_PROTECT_STATUS, &reg);

		KGSL_DRV_CRIT(device,

		KGSL_DRV_CRIT_RATELIMIT(device,

			"CP | Protected mode error| %s | addr=%x\n",

			reg & (1 << 24) ? "WRITE" : "READ",

			(reg & 0xFFFFF) >> 2);

		return;

		break;

	case A4XX_INT_CP_AHB_ERROR_HALT:

		KGSL_DRV_CRIT_RATELIMIT(device,

			"ringbuffer AHB error interrupt\n");

drivers/gpu/msm/adreno_a5xx.c

+2 −2
Original line number Diff line number Diff line
@@ -3070,7 +3070,7 @@ static void a5xx_err_callback(struct adreno_device *adreno_dev, int bit) 
		 * Return the word address of the erroring register so that it

		 * matches the register specification

		 */

		KGSL_DRV_CRIT(device,

		KGSL_DRV_CRIT_RATELIMIT(device,

			"RBBM | AHB bus error | %s | addr=%x | ports=%x:%x\n",

			reg & (1 << 28) ? "WRITE" : "READ",

			(reg & 0xFFFFF) >> 2, (reg >> 20) & 0x3,
@@ -3078,7 +3078,7 @@ static void a5xx_err_callback(struct adreno_device *adreno_dev, int bit) 


		/* Clear the error */

		kgsl_regwrite(device, A5XX_RBBM_AHB_CMD, (1 << 4));

		return;

		break;

	}

	case A5XX_INT_RBBM_TRANSFER_TIMEOUT:

		KGSL_DRV_CRIT_RATELIMIT(device, "RBBM: AHB transfer timeout\n");

drivers/gpu/msm/adreno_dispatch.c

+1 −1
Original line number Diff line number Diff line
@@ -2569,7 +2569,7 @@ void adreno_dispatcher_preempt_callback(struct adreno_device *adreno_dev, 
	struct adreno_dispatcher *dispatcher = &(adreno_dev->dispatcher);

	if (ADRENO_DISPATCHER_PREEMPT_TRIGGERED !=

			atomic_read(&dispatcher->preemption_state)) {

		KGSL_DRV_INFO(KGSL_DEVICE(adreno_dev),

		KGSL_DRV_CRIT_RATELIMIT(KGSL_DEVICE(adreno_dev),

			"Preemption interrupt generated w/o trigger!\n");

		return;

	}