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Commit b1a6018e authored by Yan He's avatar Yan He
Browse files

msm: ep_pcie: update retry counters and intervals 



Update retry counters and intervals for PCIe PHY init and PCIe link
training to accommodate various hosts.

Change-Id: I767de1f08580137559e974c0ef90273ccf5f4b76
Signed-off-by: default avatarYan He <yanhe@codeaurora.org>
parent 89917ddd

drivers/platform/msm/ep_pcie/ep_pcie_com.h

+14 −14
Original line number Diff line number Diff line
@@ -86,20 +86,20 @@ 
#define PCIE20_PLR_IATU_LTAR           0x918

#define PCIE20_PLR_IATU_UTAR           0x91c



#define PERST_TIMEOUT_US_MIN	              5000

#define PERST_TIMEOUT_US_MAX	              5100

#define PERST_CHECK_MAX_COUNT		      2000

#define LINK_UP_TIMEOUT_US_MIN	              5000

#define LINK_UP_TIMEOUT_US_MAX	              5100

#define LINK_UP_CHECK_MAX_COUNT		      2000

#define BME_TIMEOUT_US_MIN	              5000

#define BME_TIMEOUT_US_MAX	              5100

#define BME_CHECK_MAX_COUNT		      6000

#define PHY_STABILIZATION_DELAY_US_MIN	      995

#define PHY_STABILIZATION_DELAY_US_MAX	      1005

#define REFCLK_STABILIZATION_DELAY_US_MIN     995

#define REFCLK_STABILIZATION_DELAY_US_MAX     1005

#define PHY_READY_TIMEOUT_COUNT               10000

#define PERST_TIMEOUT_US_MIN	              1000

#define PERST_TIMEOUT_US_MAX	              1000

#define PERST_CHECK_MAX_COUNT		      30000

#define LINK_UP_TIMEOUT_US_MIN	              1000

#define LINK_UP_TIMEOUT_US_MAX	              1000

#define LINK_UP_CHECK_MAX_COUNT		      30000

#define BME_TIMEOUT_US_MIN	              1000

#define BME_TIMEOUT_US_MAX	              1000

#define BME_CHECK_MAX_COUNT		      30000

#define PHY_STABILIZATION_DELAY_US_MIN	      1000

#define PHY_STABILIZATION_DELAY_US_MAX	      1000

#define REFCLK_STABILIZATION_DELAY_US_MIN     1000

#define REFCLK_STABILIZATION_DELAY_US_MAX     1000

#define PHY_READY_TIMEOUT_COUNT               30000

#define XMLH_LINK_UP                          0x400



#define MAX_PROP_SIZE 32

drivers/platform/msm/ep_pcie/ep_pcie_core.c

+2 −2
Original line number Diff line number Diff line
@@ -1034,7 +1034,7 @@ int ep_pcie_core_enable_endpoint(enum ep_pcie_options opt) 
		if (ep_pcie_phy_is_ready(dev))

			break;

		retries++;

		if (retries % 10 == 0)

		if (retries % 100 == 0)

			EP_PCIE_DBG(dev,

				"PCIe V%d: current number of PHY retries:%d.\n",

				dev->rev, retries);
@@ -1069,7 +1069,7 @@ int ep_pcie_core_enable_endpoint(enum ep_pcie_options opt) 
		usleep_range(LINK_UP_TIMEOUT_US_MIN, LINK_UP_TIMEOUT_US_MAX);

		val =  readl_relaxed(dev->elbi + PCIE20_ELBI_SYS_STTS);

		retries++;

		if (retries % 5 == 0)

		if (retries % 100 == 0)

			EP_PCIE_DBG(dev, "PCIe V%d: LTSSM_STATE:0x%x.\n",

					dev->rev, (val >> 0xC) & 0x3f);

	} while ((!(val & XMLH_LINK_UP) ||