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Commit b18ea4dc authored by Thomas Petazzoni's avatar Thomas Petazzoni Committed by Jason Cooper
Browse files

ARM: dts: mvebu: move all peripherals inside soc 



reorganize the .dts and .dtsi files so that all devices are under the
soc { } node (currently some devices such as the interrupt controller,
the L2 cache and a few others are outside).

Signed-off-by: default avatarThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: default avatarJason Cooper <jason@lakedaemon.net>
parent 1b2529d0

arch/arm/boot/dts/armada-370-xp.dtsi

+13 −13
Original line number Diff line number Diff line
@@ -28,6 +28,13 @@ 
		};

	};



	soc {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "simple-bus";

		interrupt-parent = <&mpic>;

		ranges;



		mpic: interrupt-controller@d0020000 {

			compatible = "marvell,mpic";

			#interrupt-cells = <1>;
@@ -41,13 +48,6 @@ 
			      <0xd0021810 0x1c>;

		};



	soc {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "simple-bus";

		interrupt-parent = <&mpic>;

		ranges;



		serial@d0012000 {

				compatible = "snps,dw-apb-uart";

				reg = <0xd0012000 0x100>;

arch/arm/boot/dts/armada-370.dtsi

+12 −11
Original line number Diff line number Diff line
@@ -20,12 +20,6 @@ 
/ {

	model = "Marvell Armada 370 family SoC";

	compatible = "marvell,armada370", "marvell,armada-370-xp";

	L2: l2-cache {

		compatible = "marvell,aurora-outer-cache";

		reg = <0xd0008000 0x1000>;

		cache-id-part = <0x100>;

		wt-override;

	};



	aliases {

		gpio0 = &gpio0;
@@ -33,17 +27,24 @@ 
		gpio2 = &gpio2;

	};



	soc {

		mpic: interrupt-controller@d0020000 {

			reg = <0xd0020a00 0x1d0>,

			      <0xd0021870 0x58>;

		};



	soc {

		system-controller@d0018200 {

				compatible = "marvell,armada-370-xp-system-controller";

				reg = <0xd0018200 0x100>;

		};



		L2: l2-cache {

			compatible = "marvell,aurora-outer-cache";

			reg = <0xd0008000 0x1000>;

			cache-id-part = <0x100>;

			wt-override;

		};



		pinctrl {

			compatible = "marvell,mv88f6710-pinctrl";

			reg = <0xd0018000 0x38>;

arch/arm/boot/dts/armada-xp.dtsi

+16 −16
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ 
	model = "Marvell Armada XP family SoC";

	compatible = "marvell,armadaxp", "marvell,armada-370-xp";



	soc {

		L2: l2-cache {

			compatible = "marvell,aurora-system-cache";

			reg = <0xd0008000 0x1000>;
@@ -40,7 +41,6 @@ 
			      <0xd0020800 0x20>;

		};



	soc {

		serial@d0012200 {

				compatible = "snps,dw-apb-uart";

				reg = <0xd0012200 0x100>;