Loading arch/arm/boot/dts/qcom/mdmfermium-bus.dtsi +15 −1 Original line number Diff line number Diff line Loading @@ -33,6 +33,13 @@ clock-names = "bus_clk", "bus_a_clk"; clocks = <&clock_gcc clk_bimc_msmbus_clk>, <&clock_gcc clk_bimc_msmbus_a_clk>; coresight-id = <203>; coresight-name = "coresight-bimc"; coresight-nr-inports = <0>; coresight-outports = <0>; coresight-child-list = <&funnel_in0>; coresight-child-ports = <3>; }; fab_pcnoc: fab-pcnoc { Loading @@ -47,6 +54,13 @@ clock-names = "bus_clk", "bus_a_clk"; clocks = <&clock_gcc clk_pcnoc_msmbus_clk>, <&clock_gcc clk_pcnoc_msmbus_a_clk>; coresight-id = <201>; coresight-name = "coresight-pcnoc"; coresight-nr-inports = <0>; coresight-outports = <0>; coresight-child-list = <&funnel_in2>; coresight-child-ports = <0>; }; /*Masters*/ Loading Loading
arch/arm/boot/dts/qcom/mdmfermium-bus.dtsi +15 −1 Original line number Diff line number Diff line Loading @@ -33,6 +33,13 @@ clock-names = "bus_clk", "bus_a_clk"; clocks = <&clock_gcc clk_bimc_msmbus_clk>, <&clock_gcc clk_bimc_msmbus_a_clk>; coresight-id = <203>; coresight-name = "coresight-bimc"; coresight-nr-inports = <0>; coresight-outports = <0>; coresight-child-list = <&funnel_in0>; coresight-child-ports = <3>; }; fab_pcnoc: fab-pcnoc { Loading @@ -47,6 +54,13 @@ clock-names = "bus_clk", "bus_a_clk"; clocks = <&clock_gcc clk_pcnoc_msmbus_clk>, <&clock_gcc clk_pcnoc_msmbus_a_clk>; coresight-id = <201>; coresight-name = "coresight-pcnoc"; coresight-nr-inports = <0>; coresight-outports = <0>; coresight-child-list = <&funnel_in2>; coresight-child-ports = <0>; }; /*Masters*/ Loading