Merge "msm: kgsl: Disable all HW clockgating during snapshot" (b067a3cf) · Commits · e / devices / android_kernel_xiaomi_markw

drivers/gpu/msm/adreno_a5xx.c

+22 −17

Original line number	Original line	Diff line number	Diff line
	@@ -1191,7 +1191,7 @@ static const struct {
	{ adreno_is_a506, a50x_hwcg_regs, ARRAY_SIZE(a50x_hwcg_regs) },		{ adreno_is_a506, a50x_hwcg_regs, ARRAY_SIZE(a50x_hwcg_regs) },
	};		};

	static void a5xx_hwcg_init(struct adreno_device *adreno_dev)		void a5xx_hwcg_set(struct adreno_device *adreno_dev, bool on)
	{		{
	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);		struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
	const struct kgsl_hwcg_reg *regs;		const struct kgsl_hwcg_reg *regs;
	@@ -1211,11 +1211,11 @@ static void a5xx_hwcg_init(struct adreno_device *adreno_dev)
	regs = a5xx_hwcg_registers[i].regs;		regs = a5xx_hwcg_registers[i].regs;

	for (j = 0; j < a5xx_hwcg_registers[i].count; j++)		for (j = 0; j < a5xx_hwcg_registers[i].count; j++)
	kgsl_regwrite(device, regs[j].off, regs[j].val);		kgsl_regwrite(device, regs[j].off, on ? regs[j].val : 0);

	/* enable top level HWCG */		/* enable top level HWCG */
	kgsl_regwrite(device, A5XX_RBBM_CLOCK_CNTL, 0xAAA8AA00);		kgsl_regwrite(device, A5XX_RBBM_CLOCK_CNTL, on ? 0xAAA8AA00 : 0);
	kgsl_regwrite(device, A5XX_RBBM_ISDB_CNT, 0x00000182);		kgsl_regwrite(device, A5XX_RBBM_ISDB_CNT, on ? 0x00000182 : 0x00000180);
	}		}

	static int _read_fw2_block_header(uint32_t *header, uint32_t id,		static int _read_fw2_block_header(uint32_t *header, uint32_t id,
	@@ -2064,7 +2064,7 @@ static void a5xx_start(struct adreno_device *adreno_dev)
	/* if not in ISDB mode enable ME/PFP split notification */		/* if not in ISDB mode enable ME/PFP split notification */
	kgsl_regwrite(device, A5XX_RBBM_AHB_CNTL1, 0xA6FFFFFF);		kgsl_regwrite(device, A5XX_RBBM_AHB_CNTL1, 0xA6FFFFFF);
	/* enable HWCG */		/* enable HWCG */
	a5xx_hwcg_init(adreno_dev);		a5xx_hwcg_set(adreno_dev, true);
	}		}

	kgsl_regwrite(device, A5XX_RBBM_AHB_CNTL2, 0x0000003F);		kgsl_regwrite(device, A5XX_RBBM_AHB_CNTL2, 0x0000003F);
	@@ -2202,19 +2202,23 @@ static void spin_idle_debug(struct kgsl_device *device)
	dev_err(device->dev, " hwfault=%8.8X\n", hwfault);		dev_err(device->dev, " hwfault=%8.8X\n", hwfault);
	}		}

	static void a5xx_post_start(struct adreno_device *adreno_dev)		static int a5xx_post_start(struct adreno_device *adreno_dev)
	{		{
			int ret;
	unsigned int cmds, start;		unsigned int cmds, start;
	struct adreno_ringbuffer *rb = adreno_dev->cur_rb;		struct adreno_ringbuffer *rb = adreno_dev->cur_rb;

	if (!adreno_is_a530(adreno_dev) &&		if (!adreno_is_a530(adreno_dev) &&
	!adreno_is_preemption_enabled(adreno_dev))		!adreno_is_preemption_enabled(adreno_dev))
	return;		return 0;

	cmds = adreno_ringbuffer_allocspace(rb, 42);		cmds = adreno_ringbuffer_allocspace(rb, 42);
	if (IS_ERR_OR_NULL(cmds))		if (IS_ERR(cmds)) {
	return;		struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

			KGSL_DRV_ERR(device, "error allocating preemtion init cmds");
			return PTR_ERR(cmds);
			}
	start = cmds;		start = cmds;

	/*		/*
	@@ -2232,14 +2236,17 @@ static void a5xx_post_start(struct adreno_device *adreno_dev)
	rb->wptr = rb->wptr - (42 - (cmds - start));		rb->wptr = rb->wptr - (42 - (cmds - start));

	if (cmds == start)		if (cmds == start)
	return;		return 0;

	if (adreno_ringbuffer_submit_spin(rb, NULL, 2000)) {		ret = adreno_ringbuffer_submit_spin(rb, NULL, 2000);
			if (ret) {
	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);		struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	KGSL_DRV_ERR(device, "hw initialization failed to idle\n");		KGSL_DRV_ERR(device, "hw initialization failed to idle\n");
	kgsl_device_snapshot(device, NULL);		kgsl_device_snapshot(device, NULL);
			return ret;
	}		}
			return 0;
	}		}

	static int a5xx_gpmu_init(struct adreno_device *adreno_dev)		static int a5xx_gpmu_init(struct adreno_device *adreno_dev)
	@@ -2275,14 +2282,12 @@ static int a5xx_gpmu_init(struct adreno_device *adreno_dev)
	*/		*/
	static int a5xx_hw_init(struct adreno_device *adreno_dev)		static int a5xx_hw_init(struct adreno_device *adreno_dev)
	{		{
	int ret;		int ret = a5xx_gpmu_init(adreno_dev);

	if (a5xx_gpmu_init(adreno_dev))		if (!ret)
	return ret;		ret = a5xx_post_start(adreno_dev);

	a5xx_post_start(adreno_dev);

	return 0;		return ret;
	}		}

	static int a5xx_switch_to_unsecure_mode(struct adreno_device *adreno_dev,		static int a5xx_switch_to_unsecure_mode(struct adreno_device *adreno_dev,

drivers/gpu/msm/adreno_a5xx.h

+2 −0

Original line number	Original line	Diff line number	Diff line
	@@ -74,6 +74,8 @@ unsigned int a5xx_num_registers(void);

	void a5xx_crashdump_init(struct adreno_device *adreno_dev);		void a5xx_crashdump_init(struct adreno_device *adreno_dev);

			void a5xx_hwcg_set(struct adreno_device *adreno_dev, bool on);

	/* GPMU interrupt multiplexor */		/* GPMU interrupt multiplexor */
	#define FW_INTR_INFO (0)		#define FW_INTR_INFO (0)
	#define LLM_ACK_ERR_INTR (1)		#define LLM_ACK_ERR_INTR (1)

drivers/gpu/msm/adreno_a5xx_snapshot.c

+2 −3

Original line number	Original line	Diff line number	Diff line
	@@ -797,11 +797,10 @@ void a5xx_snapshot(struct adreno_device *adreno_dev,
	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);		struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);		struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
	struct adreno_snapshot_data *snap_data = gpudev->snapshot_data;		struct adreno_snapshot_data *snap_data = gpudev->snapshot_data;
	unsigned int clock_ctl, reg;		unsigned int reg;

	/* Disable Clock gating temporarily for the debug bus to work */		/* Disable Clock gating temporarily for the debug bus to work */
	kgsl_regread(device, A5XX_RBBM_CLOCK_CNTL, &clock_ctl);		a5xx_hwcg_set(adreno_dev, false);
	kgsl_regwrite(device, A5XX_RBBM_CLOCK_CNTL, 0);

	kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_REGS,		kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_REGS,
	snapshot, a5xx_snapshot_registers, NULL);		snapshot, a5xx_snapshot_registers, NULL);