markw: DTS: Extended list of GPU frequencies (overlay) (b05eb926) · Commits · e / devices / android_kernel_xiaomi_markw

arch/arm/boot/dts/qcom/markw/msm8953-overclock-markw.dtsi

+133 −2

Original line number	Diff line number	Diff line
		@@ -12,8 +12,8 @@
		* GNU General Public License for more details.
		*/

		/* dts for overckloc markw (for futre)*/

		/* dts for overckloc markw (for future)*/
		/* for сpu in msm8953.dtsi*/
		&soc {
		devfreq-cpufreq {
		cpubw-cpufreq {
		@@ -37,3 +37,134 @@
		};
		};
		};

		/* msm8953-gpu.dtsi */
		&soc {
		msm_gpu: qcom,kgsl-3d0@1c00000 {
		qcom,initial-pwrlevel = <7>;
		};

		msm_gpu: qcom,kgsl-3d0@1c00000 {
		qcom,ca-target-pwrlevel = <3>;
		};

		msm_gpu: qcom,kgsl-3d0@1c00000 {
		qcom,gpu-pwrlevels {
		#address-cells = <1>;
		#size-cells = <0>;

		compatible = "qcom,gpu-pwrlevels";

		/* TURBO+ */
		qcom,gpu-pwrlevel@0 {
		reg = <0>;
		qcom,gpu-freq = <700000000>;
		qcom,bus-freq = <10>;
		qcom,bus-min = <10>;
		qcom,bus-max = <10>;
		};

		/* TURBO */
		qcom,gpu-pwrlevel@1 {
		reg = <1>;
		qcom,gpu-freq = <650000000>;
		qcom,bus-freq = <10>;
		qcom,bus-min = <9>;
		qcom,bus-max = <10>;
		};

		/* NOM+ */
		qcom,gpu-pwrlevel@2 {
		reg = <2>;
		qcom,gpu-freq = <560000000>;
		qcom,bus-freq = <10>;
		qcom,bus-min = <8>;
		qcom,bus-max = <10>;
		};

		/* NOM */
		qcom,gpu-pwrlevel@3 {
		reg = <3>;
		qcom,gpu-freq = <510000000>;
		qcom,bus-freq = <9>;
		qcom,bus-min = <6>;
		qcom,bus-max = <10>;
		};

		/* SVS+ */
		qcom,gpu-pwrlevel@4 {
		reg = <4>;
		qcom,gpu-freq = <400000000>;
		qcom,bus-freq = <8>;
		qcom,bus-min = <5>;
		qcom,bus-max = <9>;
		};

		/* SVS */
		qcom,gpu-pwrlevel@5 {
		reg = <5>;
		qcom,gpu-freq = <320000000>;
		qcom,bus-freq = <7>;
		qcom,bus-min = <4>;
		qcom,bus-max = <8>;
		};

		/* Low SVS */
		qcom,gpu-pwrlevel@6 {
		reg = <6>;
		qcom,gpu-freq = <216000000>;
		qcom,bus-freq = <5>;
		qcom,bus-max = <6>;
		qcom,bus-min = <2>;
		};

		/* Min SVS */
		qcom,gpu-pwrlevel@7 {
		reg = <7>;
		qcom,gpu-freq = <100000000>;
		qcom,bus-freq = <2>;
		qcom,bus-min = <1>;
		qcom,bus-max = <4>;
		};

		/* XO */
		qcom,gpu-pwrlevel@8 {
		reg = <8>;
		qcom,gpu-freq = <19200000>;
		qcom,bus-freq = <0>;
		qcom,bus-min = <0>;
		qcom,bus-max = <0>;
		};
		};
		};
		};

		/* for gpu in msm8953-regulator.dtsi*/
		&soc {
		gfx_vreg_corner: ldo@0185f000 {
		regulator-max-microvolt = <8>;
		};
		};

		/* for gpu in msm8953.dtsi*/
		&soc {
		qcom,msm-thermal {
		qcom,vdd-gfx-rstr {
		qcom,levels = <5 7 8>; /* Nominal, Turbo, Turbo+ */
		};
		};

		clock_gcc_gfx: qcom,gcc-gfx@1800000 {
		qcom,gfxfreq-corner =
		< 0 0 >,
		< 100000000 1 >, /* Min SVS */
		< 216000000 2 >, /* Low SVS */
		< 320000000 3 >, /* SVS */
		< 400000000 4 >, /* SVS+ */
		< 510000000 5 >, /* NOM */
		< 560000000 6 >, /* Nom+ */
		< 650000000 7 >, /* Turbo */
		< 700000000 8 >; /* Turbo+ */
		#clock-cells = <1>;
		};
		};