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Commit b00d533e authored by Dong Aisheng's avatar Dong Aisheng Committed by Sascha Hauer
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ARM: mxs: correct the using of frac div for saif



According to spec, set to 1 is the enable of fractional devide
or the clock can not be generated properly.

Signed-off-by: default avatarDong Aisheng <b29396@freescale.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: default avatarWolfram Sang <w.sang@pengutronix.de>
parent ce9b8e6f
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+2 −2
Original line number Diff line number Diff line
@@ -710,11 +710,11 @@ static int clk_misc_init(void)

	/* SAIF has to use frac div for functional operation */
	reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0);
	reg &= ~BM_CLKCTRL_SAIF0_DIV_FRAC_EN;
	reg |= BM_CLKCTRL_SAIF0_DIV_FRAC_EN;
	__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0);

	reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1);
	reg &= ~BM_CLKCTRL_SAIF1_DIV_FRAC_EN;
	reg |= BM_CLKCTRL_SAIF1_DIV_FRAC_EN;
	__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1);

	/*