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Commit afffb9df authored by Keith Packard's avatar Keith Packard
Browse files

drm/i915: All PCH refclks are 120MHz 



I can't find any reference clocks which run at 96MHz as seems to be
indicated from the comments in this code.

Signed-off-by: default avatarKeith Packard <keithp@keithp.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent 99eb6a01

drivers/gpu/drm/i915/intel_display.c

+4 −10
Original line number Diff line number Diff line
@@ -5281,16 +5281,10 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, 
		num_connectors++;

	}



	if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {

		refclk = dev_priv->lvds_ssc_freq * 1000;

		DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",

			      refclk / 1000);

	} else {

		refclk = 96000;

		if (!has_edp_encoder ||

		    intel_encoder_is_pch_edp(&has_edp_encoder->base))

			refclk = 120000; /* 120Mhz refclk */

	}

	/*

	 * Every reference clock in a PCH system is 120MHz

	 */

	refclk = 120000;



	/*

	 * Returns a set of divisors for the desired target clock with the given