Loading drivers/platform/msm/ipa/ipa_v2/ipa_hdr.c +36 −35 Original line number Diff line number Diff line Loading @@ -600,12 +600,12 @@ static int __ipa_add_hdr_proc_ctx(struct ipa_hdr_proc_ctx_add *proc_ctx, mem_size = (ipa_ctx->hdr_proc_ctx_tbl_lcl) ? IPA_MEM_PART(apps_hdr_proc_ctx_size) : IPA_MEM_PART(apps_hdr_proc_ctx_size_ddr); if (list_empty(&htbl->head_free_offset_list[bin])) { if (htbl->end + ipa_hdr_proc_ctx_bin_sz[bin] > mem_size) { IPAERR("hdr proc ctx table overflow\n"); goto bad_len; } if (list_empty(&htbl->head_free_offset_list[bin])) { offset = kmem_cache_zalloc(ipa_ctx->hdr_proc_ctx_offset_cache, GFP_KERNEL); if (!offset) { Loading Loading @@ -711,6 +711,7 @@ static int __ipa_add_hdr(struct ipa_hdr_add *hdr) mem_size = (ipa_ctx->hdr_tbl_lcl) ? IPA_MEM_PART(apps_hdr_size) : IPA_MEM_PART(apps_hdr_size_ddr); if (list_empty(&htbl->head_free_offset_list[bin])) { /* * if header does not fit to table, place it in DDR * This is valid for IPA 2.5 and on, Loading @@ -728,13 +729,12 @@ static int __ipa_add_hdr(struct ipa_hdr_add *hdr) DMA_TO_DEVICE); if (dma_mapping_error(ipa_ctx->pdev, entry->phys_base)) { IPAERR("dma_map_single failure for entry\n"); IPAERR("dma_map_single failureed\n"); goto fail_dma_mapping; } } } else { entry->is_hdr_proc_ctx = false; if (list_empty(&htbl->head_free_offset_list[bin])) { offset = kmem_cache_zalloc(ipa_ctx->hdr_offset_cache, GFP_KERNEL); if (!offset) { Loading @@ -751,14 +751,15 @@ static int __ipa_add_hdr(struct ipa_hdr_add *hdr) htbl->end += ipa_hdr_bin_sz[bin]; list_add(&offset->link, &htbl->head_offset_list[bin]); entry->offset_entry = offset; } } else { entry->is_hdr_proc_ctx = false; /* get the first free slot */ offset = list_first_entry(&htbl->head_free_offset_list[bin], struct ipa_hdr_offset_entry, link); list_move(&offset->link, &htbl->head_offset_list[bin]); } entry->offset_entry = offset; } Loading drivers/platform/msm/ipa/ipa_v3/ipa_hdr.c +27 −26 Original line number Diff line number Diff line Loading @@ -374,12 +374,12 @@ static int __ipa_add_hdr_proc_ctx(struct ipa_hdr_proc_ctx_add *proc_ctx, mem_size = (ipa3_ctx->hdr_proc_ctx_tbl_lcl) ? IPA_MEM_PART(apps_hdr_proc_ctx_size) : IPA_MEM_PART(apps_hdr_proc_ctx_size_ddr); if (list_empty(&htbl->head_free_offset_list[bin])) { if (htbl->end + ipa_hdr_proc_ctx_bin_sz[bin] > mem_size) { IPAERR("hdr proc ctx table overflow\n"); goto bad_len; } if (list_empty(&htbl->head_free_offset_list[bin])) { offset = kmem_cache_zalloc(ipa3_ctx->hdr_proc_ctx_offset_cache, GFP_KERNEL); if (!offset) { Loading Loading @@ -484,6 +484,7 @@ static int __ipa_add_hdr(struct ipa_hdr_add *hdr) mem_size = (ipa3_ctx->hdr_tbl_lcl) ? IPA_MEM_PART(apps_hdr_size) : IPA_MEM_PART(apps_hdr_size_ddr); if (list_empty(&htbl->head_free_offset_list[bin])) { /* if header does not fit to table, place it in DDR */ if (htbl->end + ipa_hdr_bin_sz[bin] > mem_size) { entry->is_hdr_proc_ctx = true; Loading @@ -491,13 +492,13 @@ static int __ipa_add_hdr(struct ipa_hdr_add *hdr) entry->hdr, entry->hdr_len, DMA_TO_DEVICE); if (dma_mapping_error(ipa3_ctx->pdev, entry->phys_base)) { if (dma_mapping_error(ipa3_ctx->pdev, entry->phys_base)) { IPAERR("dma_map_single failure for entry\n"); goto fail_dma_mapping; } } else { entry->is_hdr_proc_ctx = false; if (list_empty(&htbl->head_free_offset_list[bin])) { offset = kmem_cache_zalloc(ipa3_ctx->hdr_offset_cache, GFP_KERNEL); if (!offset) { Loading @@ -514,14 +515,14 @@ static int __ipa_add_hdr(struct ipa_hdr_add *hdr) htbl->end += ipa_hdr_bin_sz[bin]; list_add(&offset->link, &htbl->head_offset_list[bin]); entry->offset_entry = offset; } } else { entry->is_hdr_proc_ctx = false; /* get the first free slot */ offset = list_first_entry(&htbl->head_free_offset_list[bin], offset = list_first_entry(&htbl->head_free_offset_list[bin], struct ipa_hdr_offset_entry, link); list_move(&offset->link, &htbl->head_offset_list[bin]); } entry->offset_entry = offset; } Loading Loading
drivers/platform/msm/ipa/ipa_v2/ipa_hdr.c +36 −35 Original line number Diff line number Diff line Loading @@ -600,12 +600,12 @@ static int __ipa_add_hdr_proc_ctx(struct ipa_hdr_proc_ctx_add *proc_ctx, mem_size = (ipa_ctx->hdr_proc_ctx_tbl_lcl) ? IPA_MEM_PART(apps_hdr_proc_ctx_size) : IPA_MEM_PART(apps_hdr_proc_ctx_size_ddr); if (list_empty(&htbl->head_free_offset_list[bin])) { if (htbl->end + ipa_hdr_proc_ctx_bin_sz[bin] > mem_size) { IPAERR("hdr proc ctx table overflow\n"); goto bad_len; } if (list_empty(&htbl->head_free_offset_list[bin])) { offset = kmem_cache_zalloc(ipa_ctx->hdr_proc_ctx_offset_cache, GFP_KERNEL); if (!offset) { Loading Loading @@ -711,6 +711,7 @@ static int __ipa_add_hdr(struct ipa_hdr_add *hdr) mem_size = (ipa_ctx->hdr_tbl_lcl) ? IPA_MEM_PART(apps_hdr_size) : IPA_MEM_PART(apps_hdr_size_ddr); if (list_empty(&htbl->head_free_offset_list[bin])) { /* * if header does not fit to table, place it in DDR * This is valid for IPA 2.5 and on, Loading @@ -728,13 +729,12 @@ static int __ipa_add_hdr(struct ipa_hdr_add *hdr) DMA_TO_DEVICE); if (dma_mapping_error(ipa_ctx->pdev, entry->phys_base)) { IPAERR("dma_map_single failure for entry\n"); IPAERR("dma_map_single failureed\n"); goto fail_dma_mapping; } } } else { entry->is_hdr_proc_ctx = false; if (list_empty(&htbl->head_free_offset_list[bin])) { offset = kmem_cache_zalloc(ipa_ctx->hdr_offset_cache, GFP_KERNEL); if (!offset) { Loading @@ -751,14 +751,15 @@ static int __ipa_add_hdr(struct ipa_hdr_add *hdr) htbl->end += ipa_hdr_bin_sz[bin]; list_add(&offset->link, &htbl->head_offset_list[bin]); entry->offset_entry = offset; } } else { entry->is_hdr_proc_ctx = false; /* get the first free slot */ offset = list_first_entry(&htbl->head_free_offset_list[bin], struct ipa_hdr_offset_entry, link); list_move(&offset->link, &htbl->head_offset_list[bin]); } entry->offset_entry = offset; } Loading
drivers/platform/msm/ipa/ipa_v3/ipa_hdr.c +27 −26 Original line number Diff line number Diff line Loading @@ -374,12 +374,12 @@ static int __ipa_add_hdr_proc_ctx(struct ipa_hdr_proc_ctx_add *proc_ctx, mem_size = (ipa3_ctx->hdr_proc_ctx_tbl_lcl) ? IPA_MEM_PART(apps_hdr_proc_ctx_size) : IPA_MEM_PART(apps_hdr_proc_ctx_size_ddr); if (list_empty(&htbl->head_free_offset_list[bin])) { if (htbl->end + ipa_hdr_proc_ctx_bin_sz[bin] > mem_size) { IPAERR("hdr proc ctx table overflow\n"); goto bad_len; } if (list_empty(&htbl->head_free_offset_list[bin])) { offset = kmem_cache_zalloc(ipa3_ctx->hdr_proc_ctx_offset_cache, GFP_KERNEL); if (!offset) { Loading Loading @@ -484,6 +484,7 @@ static int __ipa_add_hdr(struct ipa_hdr_add *hdr) mem_size = (ipa3_ctx->hdr_tbl_lcl) ? IPA_MEM_PART(apps_hdr_size) : IPA_MEM_PART(apps_hdr_size_ddr); if (list_empty(&htbl->head_free_offset_list[bin])) { /* if header does not fit to table, place it in DDR */ if (htbl->end + ipa_hdr_bin_sz[bin] > mem_size) { entry->is_hdr_proc_ctx = true; Loading @@ -491,13 +492,13 @@ static int __ipa_add_hdr(struct ipa_hdr_add *hdr) entry->hdr, entry->hdr_len, DMA_TO_DEVICE); if (dma_mapping_error(ipa3_ctx->pdev, entry->phys_base)) { if (dma_mapping_error(ipa3_ctx->pdev, entry->phys_base)) { IPAERR("dma_map_single failure for entry\n"); goto fail_dma_mapping; } } else { entry->is_hdr_proc_ctx = false; if (list_empty(&htbl->head_free_offset_list[bin])) { offset = kmem_cache_zalloc(ipa3_ctx->hdr_offset_cache, GFP_KERNEL); if (!offset) { Loading @@ -514,14 +515,14 @@ static int __ipa_add_hdr(struct ipa_hdr_add *hdr) htbl->end += ipa_hdr_bin_sz[bin]; list_add(&offset->link, &htbl->head_offset_list[bin]); entry->offset_entry = offset; } } else { entry->is_hdr_proc_ctx = false; /* get the first free slot */ offset = list_first_entry(&htbl->head_free_offset_list[bin], offset = list_first_entry(&htbl->head_free_offset_list[bin], struct ipa_hdr_offset_entry, link); list_move(&offset->link, &htbl->head_offset_list[bin]); } entry->offset_entry = offset; } Loading